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| 80225 4-1 md400182/a 1 80225 10/100 mbpstx/10bt ethernet physical layer device (phy) features n single chip 100base-tx /10base-t physical layer solution n 3.3v version of seeq 80221 n dual speed - 10/100 mbps n half and full duplex n mii interface to ethernet controller n mi interface for configuration & status n optional repeater interface n autonegotiation: 10/100, full/half duplex n meets all applicable ieee 802.3 standards n advertisement control through pins n on chip wave shaping - no external filters required n adaptive equalizer n baseline wander correction n led outputs - link - activity - collision - full duplex - 10/100 n many user features and options n few external components n 3.3v supply with 5v tolerant i/o n 44 plcc 99025 description the 80225 is a highly integrated analog interface ic for twisted pair ethernet applications. the 80225 can be configured for either (100base-tx) or 10 mbps (10base- t) ethernet operation. the 80225 consist of 4b5b/manchester encoder/decoder, scrambler/descrambler, transmitter with wave shaping and output driver, twisted pair receiver with on chip equal- izer and baseline wander correction, clock and data recov- ery, autonegotiation, controller interface (mii), and serial port (mi). the addition of internal output waveshaping circuitry and on-chip filters eliminates the need for external filters nor- mally required in 100base-tx and 10base-t applications. the 80225 can automatically configure itself for 100 or 10 mbps and full or half duplex operation with the on-chip autonegotiation algorithm. the 80225 can access six 16-bit registers though the management interface (mi) serial port. these registers contain configuration inputs, status outputs, and device capabilities. the 80225 is ideal as a media interface for 100base-tx/ 10base-t adapter cards, motherboards, repeaters, switch- ing hubs, and external phy's. the 80225 operates from a single 3.3v supply. all inputs and outputs are 5v tolerant and will directly interface to other 5v devices. note: check for latest data sheet revision before starting any designs. seeq data sheets are now on the web, at www.lsilogic.com. this document is an lsi logic document. any reference to seeq technology should be considered lsi logic.
80225 md400182/a 2 pin configuration 80225 top view 44l plcc 8 7 9 13 12 11 10 14 15 la_led/(mda3) crs col mdio gnd3 speed c_led/(mda2) rx_er 17 16 rx_dv tx_en gnd4 oscin rext 37 38 39 36 tx_clk 32 33 34 35 31 29 30 tx_er txd3 txd2 txd1 txd0 gnd2 fd_led/(mda1) aneg tpi duplx tpi+ 40 41 44 1 43 42 2 6 5 4 3 21 22 18 rptr gnd5 rxd0 rxd1 20 19 rxd3 rxd2 vdd3 25 24 23 26 27 rx_clk rx_en 28 vdd4 vdd2 mdc gnd6 reset l_led/(mda0) vdd1 tpo tpo+ gnd1 80225 4-3 md400182/a 3 pin # pin i/o description name 28 vdd4 positive supply. 3.3v 5% volts 24 vdd3 10 vdd2 1 vdd1 27 gnd6 ground. 0 volts 22 gnd5 36 gnd4 9 gnd3 4 gnd2 41 gnd1 43 tpo+ o twisted pair transmit output, positive. 44 tpo - o twist[d pair transmit output, negative. 2 tpi+ i twisted pair receive input, positive. 3 tpi - i twisted pair receive input, negative. 39 rext transmit current set. an external resistor connected between this pin and gnd will set the output current for the tp and fx transmit outputs. 37 oscin i clock oscillator input. there must be either a 25 mhz crystal between this pin and gnd or a 25 mhz clock applied to this pin. tx_clk output is generated from this input. 29 tx_clk o transmit clock output. this controller interface output provides a clock to an external controller. transmit data from the controller on txd, tx_en, and tx_er is clocked in on rising edges of tx_clk and oscin. 35 tx_en i transmit enable input. this controller interface input has to be asserted active high to indicate that data on txd and tx_er is valid, and it is clocked in on rising edges of tx_clk and oscin. 33 txd3 i transmit data input. these controller interface inputs contain input nibble data to be 32 txd2 transmitted on the tp outputs, and they are clocked in on rising edges of tx_clk and oscin 31 txd1 when tx_en is asserted. 30 txd0 34 tx_er i transmit error input. this controller interface input causes a special pattern to be transmitted on the twisted pair outputs in place of normal data, and it is clocked in on rising edges of tx_clk when tx_en is asserted. 25 rx_clk o receive clock output. this controller interface output provides a clock to an external controller. receive data on rxd, rx_dv, and rx_er is clocked out on falling edges of rx_clk. 15 crs o carrier sense output. this controller interface output is asserted active high when valid data is detected on the receive twisted pair inputs, and it is clocked out on falling edges of rx_clk. 16 rx_dv o receive data valid output. this controller interface output is asserted active high when valid decoded data is present on the rxd outputs, and it is clocked out on falling edges of rx_clk. 18 rxd3 o receive data output. these controller interface outputs contain receive nibble data from 19 rxd2 the tp input, and they are clocked out on falling edges of rx_clk. 20 rxd1 21 rxd0 1.0 pin description 80225 md400182/a 4 17 rx_er o receive error output. this controller interface output is asserted active high when a coding or other specified errors are detected on the receive twisted pair inputs and it is clocked out on falling edges of rx_clk. 14 col o collision output. this controller interface output is asserted active high when a collision between transmit and receive data is detected. 12 mdc i management interface (mi) clock input. this mi clock shifts serial data into and out of mdio on rising edges. 13 mdio i/o management interface (mi) data input/output. this bidirectional pin contains serial mi data that is clocked in and out on rising edges of the mdc clock. 8 la_led/ i/o (mda3) o.d. pullup 7 c_led/ i/o (mda2) o.d. pullup 6 fd_led/ i/o (mda1) pullup 5 l_led/ i/o (mda0) pullup link led output/management interface address input. the function of this pin is to be a 10/100 mbps detect output. this pin can drive an led from vdd. 0 = 100 mbit mode detected with link pass 1 = 10 mbit mode detected during powerup or reset, this pin is high impedance and the value on this pin is latched in as the address mda0 for the mi serial port. pin description continued pin # pin i/o description name link + activity led/management interface address input. the function of this pin is to indicate the occurrence of link or activity. this pin can drive an led from vdd. 0 = link detect blink = link detect and activity 1 = no link detect during powerup or reset, this pin is high impedance and the value on this pin is latched inas the physical device address mda3 for the mi serial port. collision led output/management interface address input. the function of this pin is to indicate the occurrence of a collision. this pin can drive an led from vdd. 0 = collision detect 1 = no collision during powerup or reset, this pin is high impedance and the value on this pin is latched in as the physical device address mda2 for the mi serial port. full duplex led output/management interface address input. the function of this pin is to be a full duplex detect output. this pin can drive an led from vdd. 0 = full duplex mode detect with link pass 1 = half duplex during powerup or reset, this pin is high impedance and the value on this pin is latched in as the physical address device address mda1 for the mi serial port. 80225 4-5 md400182/a 5 26 rx_en i receive enable input 1 = all outputs enabled 0 = receive controller outputs are high impedance (rx_clk, rxd[3:0], rx_dv, rx_er, col). 23 rptr i repeater mode enable input. 1 = repeater mode enabled 0 = normal operation 11 speed i speed select input. this input pin selects 10/100 mbps operation when pin aneg = 0. when aneg = 1, this pin controls the 10/100 advertisement abilities of the device. 1 = 100 mbps 0 = 10 mbps 42 dplx i full/half duplex select input. this input pin selects half/full duplex operation when pin aneg = 0. when aneg = 1, this pin controls the half/full duplex advertisement ablilities. 1 = full duplex 0 = half duplex 40 aneg i autonegotiation enable input. 1 = autonegotiation on 0 = autonegotiation off aneg speed duplx 0 0 0 forced 10 mbit half duplex mode 0 0 1 forced 10 mbit full duplex mode 0 1 0 forced 100 mbit half duplex mode 0 1 1 forced 100 mbit full dulex mode 1 0 0 autonegotiate and advertise 10 m half duplex only 1 0 1 autonegotiate and advertise 10 m half/full duplex only 1 1 0 autonegotiate and advertise all the capabilities mode (default). note: to control advertisement through the register, these three pins have to be configured in this default mode. 1 1 1 autonegotiate and advertise 10/100 m half duplex only 38 reset i reset input pullup 1 = normal operation 0 = device reset pin # pin i/o description name pin description continued 80225 md400182/a 6 2.0 block diagram tx_clk tx_er tx_en txd[3:0] controller interface (mii) col rx_clk rx_er rx_dv rxd[3:0] crs serial port (mi) mdc mdio led drivers led[3:0] gnd[6:1] vdd[4:1] collision oscillator oscin (mda[3:0]) lp filter rom dac + 10baset transmitter clock gen (pll) manchester encoder 4b5b encoder scrambler tpo+ switched current sources + 100basetx transmitter clock gen (pll) tpo lp filter mlt3 encoder 4b5b decoder descrambler clock & data recovery auto- negotiation & link squelch clock & data recovery (manchester decoder) tpi+ tpi lp filter + +/?vth + 10baset receiver figure 1. 80225 block diagram adaptive equalizer + +/?vth + 100basetx receiver mlt3 encoder squelch dplx speed aneg rext rx_en rptr reset 80225 4-7 md400182/a 7 3.0 functional description 3.1 general the 80225 is a complete 100/10 mbps ethernet media interface ic. the 80225 has nine main sections: controller interface, encoder, decoder, scrambler, descrambler, clock and data recovery, twisted pair transmitter, twisted pair receiver, and mi serial port. a block diagram is shown in figure 1. the 80225 can operate as a 100base-tx device (hereaf- ter referred to as 100 mbps mode) or as a 10base-t device (hereafter referred to as 10 mbps mode). the difference between the 100 mbps mode and the 10 mbps mode is data rate, signalling protocol, and allowed wiring. the 100 mbps tx mode uses two pairs of category 5 or better utp or stp twisted pair cable with 4b5b encoded, scrambled, and mlt-3 coded 62.5 mhz ternary data to achieve a thruput of 100 mbps. the 10 mbps mode uses two pairs of category 3 or better utp or stp twisted pair cable with manchester encoded, 10 mhz binary data to achieve a 10 mbps thruput. the data symbol format on the twisted pair cable for the 100 and 10 mbps modes are defined in ieee 802.3 specifications and shown in figure 2. on the transmit side for 100 mbps tx operation, data is received on the controller interface from an external ethernet controller per the format shown in figure 3. the data is then sent to the 4b5b encoder for formatting. the encoded data is then sent to the scrambler. the scrambled and encoded data is then sent to the tp transmitter. the tp transmitter converts the encoded and scrambled data into mlt-3 ternary format, preshapes the output, and drives the twisted pair cable. figure 2. tx/10bt frame format preamble sfd da llc data fcs sa interframe gap ethernet mac frame ln interframe gap ssd preamble sfd llc data fcs da idle 100 base-tx data symbols sa idle ln esd = [ 1 1 1 1 ...] = [ 0 1 1 0 1 0 0 1 1 1 ] = [ data ] = [ 1 1 ] = [ 1 0 1 0 ...] 62 bits long = [ 1 1 0 0 0 1 0 0 0 1 ] esd da, sa, ln, llc data, fcs ssd preamble sfd idle before / after 4b5b encoding, scrambling, and mlt3 coding preamble sfd llc data fcs da idle 10 base-t data symbols sa idle ln soi = [ no transitions ] = [ 1 1 ] with no mid bit transition = [ data ] = [ 1 1 ] = [ 1 0 1 0 ... ] 62 bits long soi da, sa, ln, llc data, fcs sfd preamble idle before / after manchester encoding ssd preamble sfd llc data fcs da idle 100 base-fx data symbols sa idle ln esd = [ 1 1 1 1 ...] = [ 0 1 1 0 1 0 0 1 1 1 ] = [ data ] = [ 1 1 ] = [ 1 0 1 0 ...] 62 bits long = [ 1 1 0 0 0 1 0 0 0 1 ] esd da, sa, ln, llc data, fcs ssd preamble sfd idle before / after 4b5b encoding 80225 md400182/a 8 signals bit value txdo x x 1 1 11111111111111 2 1 txd1 x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 txd2 x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 txd3 x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 tx_en 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 d0 3 d4 4 d1 d5 d2 d6 d3 d7 11 1. 1st preamble nibble transmitted. 2. 1st sfd nibble transmittted. 3. 1st data nibble transmitted. 4. d0 thru d7 are the first 8 bits of the data field. signals bit value rxdo x 1 1 111111111111111 2 1 rxd1 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rxd2 x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 rxd3 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 rx_dv 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 d0 3 d4 4 d1 d5 d2 d6 d3 d7 11 1. 1st preamble nibble received. depending on mode, device may eliminate either all or some of the preamble nibbles, up to 1st sfd nibble. 2. 1st sfd nibble received. 3. 1st data nibble received. 4. d0 thru d7 are the first 8 bits of the data field. figure 3. mii frame format c.) transmit preamble and sfd bits d.) receive preamble and sfd bits a.) mii frame format b.) mii nibble order idle preamble prmble sfd data 1 data n-1 data n start of frame delim. 62 bt data 2 data nibbles 2 bt idle tx_en = 0 tx_en = 0 tx_en = 1 first nibble first bit mac? serial bit stream d0 d1 d2 d3 d4 d5 d6 d7 txd0 / rxd0 txd3 / rxd3 txd2 / rxd2 txd1 / rxd1 msb second nibble mii nibble stream lsb = tx_en = 0 = [ between 64-1518 data bytes ] = [ 1 1 ] = [ 1 0 1 0 ... ] 62 bits long idle datan sfd preamble 80225 4-9 md400182/a 9 on the receive side for 100 mbps tx operation, the twisted pair receiver receives incoming encoded and scrambled mlt-3 data from the twisted pair cable, remove any high frequency noise, equalizes the input signal to compensate for the effects of the cable, qualifies the data with a squelch algorithm, and converts the data from mlt-3 coded twisted pair levels to internal digital levels. the output of the twisted pair receiver then goes to a clock and data recov- ery block which recovers a clock from the incoming data, uses the clock to latch in valid data into the device, and converts the data back to nrz format. the nrz data is then unscrambled and decoded by the 4b5b decoder and descrambler, respectively, and outputted to an external ethernet controller by the controller interface. 10 mbps operation is similar to the 100 mbps tx operation except, (1) there is no scrambler/descrambler, (2) the encoder/decoder is manchester instead of 4b5b, (3) the data rate is 10 mbps instead of 100 mbps, and (4) the twisted pair symbol data is two level manchester instead of ternary mlt-3. the management interface, (hereafter referred to as the mi serial port), is a two pin bidirectional link through which configuration inputs can be set and status outputs can be read. each block plus the operating modes are described in more detail in the following sections. since the 80225 can operate either as a 100base-tx or a 10base-t device, each of the following sections describes the performance of the respective section in both the 100 and 10 mbps modes. 3.2 differences between 80220/80221, 80225, and 80223 table 1. 80221, 80225 and 80223 difference 80221 80225 80223 power supply 5v 3.3v 3.3v reset pin no yes yes fx interface no yes yes transmit xfmr. 2:1 1:1 1:1 winding ratio t4 interface yes no no speed pin no yes yes duplx pin no yes yes hardware no yes no advertisement control registers 16-20 yes no yes 3.3 controller interface 3.3.1 general the 80225 has two interfaces to an external controller: media independent interface (referred to as the mii). 3.3.2 mii - 100 mbps the mii is a nibble wide packet data interface defined in ieee 802.3 and shown in figure 3. the 80225 meets all the mii requirements outlined in ieee 802.3. the 80225 can directly connect, without any external logic, to any ethernet controllers or other devices which also complies with the ieee 802.3 mii specifications. the mii frame format is shown in figure 3. the mii consists of eighteen signals: four transmit data bits (txd[3:0]), transmit clock (tx_clk), transmit enable (tx_en), transmit error (tx_er), four receive data bits (rxd[3:0]), receive clock (rx_clk), carrier sense (crs), receive data valid (rx_dv), receive data error (rx_er), and collision (col). the transmit and receive clocks operate at 25 mhz in 100 mbps mode. on the transmit side, the tx_clk output runs continu- ously at 25 mhz. when no data is to be transmitted, tx_en has to be deasserted. while tx_en is deasserted, tx_er and txd[3:0] are ignored and no data is clocked into the device. when tx_en is asserted on the rising edge of tx_clk, data on txd[3:0] is clocked into the device on rising edges of the tx_clk output clock. txd[3:0] input data is nibble wide packet data whose format needs to be the same as specified in ieee 802.3 and shown in figure 3. when all data on txd[3:0] has been latched into the device, tx_en has to be deasserted on the rising edge of tx_clk. tx_er is also clocked in on rising edges of the tx_clk clock. tx_er is a transmit error signal which, when asserted, will substitute an error nibble in place of the normal data nibble that was clocked in on txd[3:0]. the error nibble is defined to be the /h/ symbol which is defined in ieee 802.3 and shown in table 2. since oscin input clock generates the tx_clk output clock, txd[3:0], tx_en, and tx_er are also clocked in on rising edges of oscin. 80225 md400182/a 10 on the receive side, as long as a valid data packet is not detected, crs and rx_dv are deasserted and rxd[3:0] is held low. when the start of packet is detected , crs and rx_dv are asserted on falling edge of rx_clk. the assertion of rx_dv indicates that valid data is clocked out on rxd[3:0] on falling edges of the rx_clk clock. the rxd[3:0] data has the same frame structure as the txd[3:0] data and is specified in ieee 802.3 and shown in figure 3. when the end of packet is detected, crs and rx_dv are deasserted, and rxd[3:0] is held low. crs and rx_dv also stay deasserted if the device is in the link fail state. rx_er is a receive error output which is asserted when certain errors are detected on a data nibble. rx_er is asserted on the falling edge of rx_clk for the duration of that rx_clk clock cycle during which the nibble contain- ing the error is being outputted on rxd[3:0]. the collision output, col, is asserted whenever the colli- sion condition is detected. 3.3.3 mii - 10 mbps 10 mbps operation is identical to the 100 mbps operation except, (1) tx_clk and rx_clk clock frequency is reduced to 2.5 mhz, (2) tx_er is ignored, (3) rx_er is disabled and always held low, and (4) receive operation is modified as follows: on the receive side, when the squelch circuit determines that invalid data is present on the tp inputs, the receiver is idle. during idle, rx_clk follows tx_clk, rxd[3:0] is held low, and crs and rx_dv are deasserted. when a start of packet is detected on the tp receive inputs, crs is asserted and the clock recovery process starts on the incoming tp input data. after the receive clock has been recovered from the data, the rx_clk is switched over to the recovered clock and the data valid signal rx_dv is asserted on a falling edge of rx_clk. once rx_dv is asserted, valid data is clocked out on rxd[3:0] on falling edges of the rx_clk clock. the rxd[3:0] data has the same packet structure as the txd[3:0] data and is formatted on rxd[3:0] as specified in ieee 802.3 and shown in figure 3. when the end of packet is detected, crs and rx_dv are deasserted. crs and rx_dv also stay deasserted as long as the device is in the link fail state. 3.3.4 mii disable the mii inputs and outputs can be disabled by setting the mii disable bit in the mi serial port control register. when the mii is disabled, the mii inputs are ignored, the mii outputs are placed in high impedance state, and the tp output is high impedance. if the mi address lines, mda[3:0], are pulled high during reset or powerup, the 80225 powers up and resets with the mii disabled. otherwise, the 80225 powers up and resets with the mii enabled. 3.3.5 receive output high impedance control the rx_en pin can be configured to be rx_en, a high impedance control for the receive controller output sig- nals, by setting the r/j configuration select bit in the mi serial port configuration 2 register. when this pin is configured to be rx_en and is deasserted active low, the following outputs will be placed in the high impedance state: rx_clk, rxd[3:0], rx_dv, rx_er, and col. 3.3.6 tx_en to crs loopback disable the internal tx_en to crs loopback can be disabled by appropriately setting the txen to crs loopback disable bit in the mi serial port configuration 1 register. 3.4 encoder 3.4.1 4b5b encoder - 100 mbps 100base-tx requires that the data be 4b5b encoded. 4b5b coding converts the 4-bit data nibbles into 5-bit date code words. the mapping of the 4b nibbles to the 5b code words is specified in ieee 802.3 and shown in table 2. the 4b5b encoder on the 80225 takes 4b nibbles from the controller interface, converts them into 5b words accord- ing to table 2, and sends the 5b words to the scrambler. the 4b5b encoder also substitutes the first 8 bits of the preamble with the ssd delimiters (a.k.a. /j/k/ symbols) and adds an esd delimiter (a.k.a /t/r/ symbols) to the end of every packet, as defined in ieee 802.3 and shown in figure 2. the 4b5b encoder also fills the period between packets, called the idle period, with the a continuous stream of idle symbols, as shown in figure 2. 3.4.2 manchester encoder - 10 mbps the manchester encoding process combines clock and nrz data such that the first half of the data bit contains the complement of the data, and the second half of the data bit contains the true data, as specified in ieee 802.3. this guarantees that a transition always occurs in the middle of the bit cell. the manchester encoder on the 80225 con- verts the 10 mbps nrz data from the controller interface into a manchester encoded data stream for the tp trans- mitter and adds a start of idle pulse (soi) at the end of the 80225 4-11 md400182/a 11 12345678901234567890123456789012123456789012345678901234567890121 1 2345678901234567890123456789012 12345678901234567890123456789012 1 1 2345678901234567890123456789012 12345678901234567890123456789012 1 1 2345678901234567890123456789012 12345678901234567890123456789012 1 1 2345678901234567890123456789012 12345678901234567890123456789012 1 12345678901234567890123456789012123456789012345678901234567890121 3.5 decoder 3.5.1 4b5b decoder - 100 mbps since the tp input data is 4b5b encoded on the transmit side, it must also be decoded by the 4b5b decoder on the receive side. the mapping of the 5b nibbles to the 4b code words is specified in ieee 802.3 and shown in table 2. the 4b45 decoder on the 80225 takes the 5b code words from the descrambler, converts them into 4b nibbles per table 2, and sends the 4b nibbles to the controller interface. the 4b5b decoder also strips off the ssd delimiter (a.k.a. /j/k/ symbols) and replaces them with two 4b data 5 nibbles (a.k.a /5/ symbol), and strips off the esd delimiter (a.k.a /t/r/ symbols) and replaces it with two 4b data 0 nibbles (a.k.a /i/ symbol), per ieee 802.3 specifi- cations and shown in figure 2. the 4b5b decoder detects ssd, esd and, codeword errors in the incoming data stream as specified in ieee 802.3. these errors are indicated by asserting rx_er output while the errors are being transmitted across rxd[3:0], and they are also indicated in the serial port by setting ssd, esd, and codeword error bits in the mi serial port status output register. 3.5.2 manchester decoder - 10 mbps in manchester coded data, the first half of the data bit contains the complement of the data, and the second half of the data bit contains the true data. the manchester decoder in the 80225 converts the manchester encoded data stream from the tp receiver into nrz data for the controller interface by decoding the data and stripping off the soi pulse. since the clock and data recovery block has already separated the clock and data from the tp receiver, the manchester decoding process to nrz data is inher- ently performed by that block. 3.6 clock and data recovery 3.6.1 clock recovery - 100 mbps clock recovery is done with a pll. if there is no valid data present on the tp inputs, the pll is locked to the 25 mhz tx_clk. when valid data is detected on the tp inputs with the squelch circuit and when the adaptive equalizer has settled, the pll input is switched to the incoming data packet as specified in ieee 802.3 and shown in figure 2. the manchester encoding process is only done on actual packet data, and the idle period between packets is not manchester encoded and filled with link pulses. table 2. 4b/5b symbol mapping symbol description 5b code 4b code name 0 data 0 11110 0000 1 data 1 01001 0001 2 data 2 10100 0010 3 data 3 10101 0011 4 data 4 01010 0100 5 data 5 01011 0101 6 data 6 01110 0110 7 data 7 01111 0111 8 data 8 10010 1000 9 data 9 10011 1001 a data a 10110 1010 b data b 10111 1011 c data c 11010 1100 d data d 11011 1101 e data e 11100 1110 f data f 11101 1111 i idle 11111 0000 j ssd #1 11000 0101 k ssd #2 10001 0101 t esd #1 01101 0000 r esd #2 00111 0000 h halt 00100 undefined --- invalid all 0000* codes others* * these 5b codes are not used. for decoder, these 5b codes are decoded to 4b 0000. for encoder, 4b 0000 is encoded to 5b 11110, as shown in symbol data 0. 1 2345678901234567890123456789012 12345678901234567890123456789012 1 1 2345678901234567890123456789012 12345678901234567890123456789012 1 1 2345678901234567890123456789012 12345678901234567890123456789012 1 1 2345678901234567890123456789012 12345678901234567890123456789012 1 12345678901234567890123456789012123456789012345678901234567890121 12345678901234567890123456789012123456789012345678901234567890121 1 2345678901234567890123456789012 12345678901234567890123456789012 1 1 2345678901234567890123456789012 12345678901234567890123456789012 1 1 2345678901234567890123456789012 12345678901234567890123456789012 1 1 2345678901234567890123456789012 12345678901234567890123456789012 1 12345678901234567890123456789012123456789012345678901234567890121 80225 md400182/a 12 on the tp input. the pll then recovers a clock by locking onto the transitions of the incoming signal from the twisted pair wire. the recovered clock frequency is a 25 mhz nibble clock, and that clock is outputted on the controller interface signal rx_clk. 3.6.2 data recovery - 100 mbps data recovery is performed by latching in data from the tp receiver with the recovered clock extracted by the pll. the data is then converted from a single bit stream into nibble wide data word according to the format shown in figure 3. 3.6.3 clock recovery - 10 mbps the clock recovery process for 10 mbps mode is identical to the 100 mbps mode except, (1) the recovered clock frequency is 2.5 mhz nibble clock, (2) the pll is switched from tx_clk to the tp input when the squelch indicates valid data, (3) the pll takes up to 12 transitions (bit times) to lock onto the preamble, so some of the preamble data symbols are lost, but the clock recovery block recovers enough preamble symbols to pass at least 6 nibbles of preamble to the receive controller interface as shown in figure 3. 3.6.4 data recovery - 10 mbps the data recovery process for 10 mbps mode is identical to the 100 mbps mode. as mentioned in the manchester decoder section, the data recovery process inherently performs decoding of manchester encoded data from the tp inputs. 3.7 scrambler 3.7.1 100 mbps 100base-tx requires scrambling to reduce the radiated emissions on the twisted pair. the 80225 scrambler takes the encoded data from the 4b5b encoder, scrambles it per the ieee 802.3 specifications, and sends it to the tp transmitter. 3.7.2 10 mpbs a scrambler is not used in 10 mbps mode. 3.8 descrambler 3.8.1 100 mbps the 80225 descrambler takes the scrambled data from the data recovery block, descrambles it per the ieee 802.3 specifications, aligns the data on the correct 5b word boundaries, and sends it to the 4b5b decoder. the algorithm for synchronization of the descrambler is the same as the algorithm outlined in the ieee 802.3 specification. once the descrambler is synchronized, it will maintain synchronization as long as enough descrambled idle pattern 1's are detected within a given interval. to stay in synchronization, the descrambler needs to detect at least 25 consecutive descrambled idle pattern 1's in a 1 ms interval. if 25 consecutive descrambled idle pattern 1's are not detected within the 1 ms interval, the descrambler goes out of synchronization and restarts the synchronization process. if the descrambler is in the unsynchronized state, the descrambler loss of synchronization detect bit is set in the mi serial port status output register to indicate this condi- tion. once this bit is set, it will stay set until the descrambler achieves synchronization. 3.8.2 10 mpbs a descrambler is not used in 10 mbps mode. 3.9 twisted pair transmitter 3.9.1 transmitter - 100 mbps the tx transmitter consists of a mlt-3 encoder, wave- form generator and line driver. the mlt-3 encoder converts the nrz data from the scrambler into a three level mlt-3 code required by ieee 802.3. mlt-3 coding uses three levels and converts 1's to transitions between the three levels, and converts 0's to no transitions or changes in level. the purpose of the waveform generator is to shape the transmit output pulse. the waveform generator takes the mlt-3 three level encoded waveform and uses an array of switched current sources to control the rise/fall time and level of the signal at the output. the output of the switched current sources then goes through a low pass filter in order to "smooth" the current output and remove any high frequency components. in this way, the waveform gen- erator preshapes the output waveform transmitted onto the twisted pair cable to meet the pulse template require- ments outlined in ieee 802.3. the waveform generator eliminates the need for any external filters on the tp transmit output. 80225 4-13 md400182/a 13 the line driver converts the shaped and smoothed wave- form to a current output that can drive 100 meters of category 5 unshielded twisted pair cable or 150 ohm shielded twisted pair cable. 3.9.2 transmitter - 10 mbps the transmitter operation in 10 mbps mode is much different than the 100 mbps transmitter. even so, the transmitter still consists of a waveform generator and line driver. the purpose of the waveform generator is to shape the output transmit pulse. the waveform generator consists of a rom, dac, clock generator, and filter. the dac generates a stair-stepped representation of the desired output waveform. the stairstepped dac output then goes through a low pass filter in order to "smooth" the dac output and remove any high frequency components. the dac values are determined from the rom outputs; the rom contents are chosen to shape the pulse to the desired template and are clocked into the dac at high speed by the clock generator. in this way, the waveform generator preshapes the output waveform to be transmit- ted onto the twisted pair cable to meet the pulse template requirements outlined in ieee 802.3 clause 14 and also shown in figure 4. the waveshaper replaces and elimi- nates external filters on the tp transmit output. the line driver converts the shaped and smoothed wave- form to a current output that can drive 100 meters of category 3/4/5 100 ohm unshielded twisted pair cable or 150 ohm shielded twisted pair cable tied directly to the tp output pins without any external filters. during the idle period, no output signal is transmitted on the tp outputs (except link pulse). 3.9.3 stp (150 ohm) cable mode the transmitter can be configured to drive 150 ohm shielded twisted pair cable. the stp mode can be selected by appropriately setting the cable type select bit in the mi serial port configuration 1 register. when stp mode is enabled, the output current is automatically ad- justed to comply with ieee 802.3 levels. 3.9.4 activity indication the la_led indicates the combination of link detect and activity. link detect 10 or 100 mb causes this led to stay on and the detection of activity causes the led to blink. whenever activity is detected. the led goes low for 100 ms every time a transmit or receive packet activity is detected. the la_led output is a open drain with a pullup resistor and can drive an led from vdd or can drive another digital input. 3.10 twisted pair receiver 3.10.1 receiver - 100 mbps the tx receiver detects input signals from the twisted pair input and convert it to a digital data bit stream ready for clock and data recovery. the receiver can reliably detect data from a 100base-tx compliant transmitter that has been passed through 0-100 meters of 100 ohm category 5 utp or 150 ohm stp. the tx receiver consists of an adaptive equalizer, baseline wander correction circuit, comparators, and mlt-3 de- coder. the tp inputs first go to an adaptive equalizer. the adaptive equalizer compensates for the low pass charac- teristic of the cable, and it has the ability to adapt and compensate for 0-100 meters of category 5,100 ohm utp or 150 ohm stp twisted pair cable. the baseline wander correction circuit restores the dc component of the input waveform that was removed by external transformers. the comparators convert the equalized signal back to digital levels and are used to qualify the data with the squelch circuit. the mlt-3 decoder takes the three level mlt-3 digital data from the comparators and converts it to back to normal digital data to be used for clock and data recovery. 3.10.2 receiver - 10 mbps the 10 mbps receiver is able to detect input signals from the twisted pair cable that are within the template shown in figure 5. the inputs are biased by internal resistors. the tp inputs pass through a low pass filter designed to eliminate any high frequency noise on the input. the output of the receive filter goes to two different types of comparators, squelch and zero crossing. the squelch comparator determines whether the signal is valid, and the zero crossing comparator is used to sense the actual data transitions once the signal is determined to be valid. the output of the squelch comparator goes to the squelch circuit and is also used for link pulse detection, soi detection, and reverse polarity detection; the output of the zero crossing comparator is used for clock and data recovery in the manchester decoder. 3.10.3 tp squelch - 100 mbps the squelch block determines if the tp input contains valid data. the 100 mbps tp squelch is one of the criteria used to determine link intergrity. the squelch comparators compare the tp inputs against fixed positive and negative 80225 md400182/a 14 0 102030405060708090100110 ?.0 ?.8 ?.6 ?.4 ?.2 0.0 0.2 0.4 0.6 0.8 1.0 time (ns) voltage (v) b c d a i j w v t g s q n o p e f m h r u l k reference time (ns) voltage (v) internal mau a00 b 15 1.0 c 15 0.4 d 25 0.55 e 32 0.45 f390 g 57 -1.0 h 48 0.7 i 67 0.6 j890 k 74 -0.55 l 73 -0.55 m61 0 n 85 1.0 o 100 0.4 p 110 0.75 q 111 0.15 r 111 0 s 111 -0.15 t 110 -1.0 u 100 -0.3 v 110 -0.7 w 90 -0.7 figure 4. tp output voltage template-10 mbps 80225 4-15 md400182/a 15 thresholds, called squelch levels. the output from the squelch comparator goes to a digital squelch circuit which determines if the receive input data on that channel is valid. if the data is invalid, the receiver is in the squelched state. if the input voltage exceeds the squelch levels at least 4 times with alternating polarity within a 10 m s interval, the data is considered to be valid by the squelch circuit and the receiver now enters into the unquelch state. in the unsquelch state, the receive threshold level is reduced by approximately 30% for noise immunity reasons and is called the unsquelch level. when the receiver is in the unsquelch state, then the input signal is deemed to be valid. the device stays in the unsquelch state until loss of data is detected. loss of data is detected if no alternating polarity unsquelch transitions are detected during any 10 m s interval. when the loss of data is detected, the receive squelch is turned on again. 3.10.4 tp squelch, 10 mbps the tp squelch algorithm for 10 mbps mode is identical to the 100 mbps mode except, (1) the 10 mbps tp squelch algorithm is not used for link integrity but to sense the beginning of a packet, (2) the receiver goes into the unsquelch state if the input voltage exceeds the squelch levels for three bit times with alternating polarity within a 50-250 ns interval, (3) the receiver goes into the squelch state when idle is detected, (4) unsquelch detection has no affect on link integrity, link pulses are used for that in 10 mbps mode, (5) start of packet is determined when the receiver goes into the unsquelch state and crs is as- serted, and (6) the receiver meets the squelch require- ments defined in ieee 802.3 clause 14. 3.11 collision 3.11.1 100 mbps collision occurs whenever transmit and receive occur simultaneously while the device is in half duplex. collision is sensed whenever there is simultaneous trans- mission (packet transmission on tpo ) and reception (non idle symbols detected on tp input). when collision is detected, the col output is asserted, tp data continues to be transmitted on twisted pair outputs, tp data continues to be received on twisted pair inputs, and internal crs loopback is disabled. once collision starts, crs is as- serted and stays asserted until the receive and transmit packets that caused the collision are terminated. the collision function is disabled if the device is in the full duplex mode, is in the link fail state, or if the device is in the diagnostic loopback mode. 3.11.2 10 mbps collision in 10 mbps mode is identical to the 100 mbps mode except, (1) reception is determined by the 10 mbps squelch criteria, (2) rxd[3:0] outputs are forced to all 0's, (3) collision is asserted when the sqe test is performed, (4) collision is asserted when the jabber condition has been detected. 3.11.3 collision test the controller interface collision signal, col, can be tested by setting the collision test register bit in the mi serial port control register. when this bit is set, tx_en is looped back onto col and the tp outputs are disabled. 3.11.4 collision indication collision is indicated through the cled pin. this pin is asserted active low for 100 ms every time a collision occurs. the cled output is open drain with pullup resistor and can drive an led from vdd or can drive another digital input. 3.12 start of packet 3.12.1 100 mbps start of packet for 100 mbps mode is indicated by a unique start of stream delimiter (referred to as ssd). the ssd pattern consists of the two /j/k/ 5b symbols inserted at the beginning of the packet in place of the first two preamble symbols, as defined in ieee 802.3 clause 24 and shown in figure 2. the transmit ssd is generated by the 4b5b encoder and the /j/k/ symbols are inserted by the 4b4b encoder at the beginning of the transmit data packet in place of the first two 5b symbols of the preamble, as shown in figure 2. the receive pattern is detected by the 4b5b decoder by examining groups of 10 consecutive code bits (two 5b words) from the descrambler. between packets, the re- ceiver will be detecting the idle pattern, which is 5b /i/ symbols. while in the idle state, crs and rx_dv are deasserted. 80225 md400182/a 16 if the receiver is in the idle state and 10 consecutive code bits from the receiver consist of the /j/k/ symbols, the start of packet is detected, data reception is begun, crs and rx_dv are asserted, and /5/5/ symbols are substituted in place of the /j/k/ symbols. if the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither /i/ i/ nor /j/k/ symbols but contains at least 2 non contiguous 0's, then activity is detected but the start of packet is considered to be faulty and a false carrier indication (also referred to as bad ssd) is signalled to the controller interface. when false carrier is detected, then crs is asserted, rx_dv remains deasserted, rxd[3:0]=1110 while rx_er is asserted, and the bad ssd bit is set in the mi serial port status output register. once a false carrier event is detected, the idle pattern (two /i/i/ symbols) must be detected before any new ssd's can be sensed. if the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither /i/ i/ nor /j/k/ symbols but does not contain at least 2 non- contiguous 0's, the data is ignored and the receiver stays in the idle state. 3.12.2 10 mbps since the idle period in 10 mbps mode is defined to be the period when no data is present on the tp inputs, then the start of packet for 10 mbps mode is detected when valid data is detected by the tp squelch circuit. when start of packet is detected, crs is asserted as described in the controller interface section. refer to the tp squelch section for 10 mbps mode for the algorithm for valid data detection. 3.13 end of packet 3.13.1 100 mbps end of packet for 100 mbps mode is indicated by a the end of stream delimiter (referred to as esd). the esd pattern consists of the two /t/r/ 4b5b symbols inserted after the end of the packet, as defined in ieee 802.3 clause 24 and shown in figure 2. the transmit esd is generated by the 4b5b encoder and the /t/r/ symbols are inserted by the 4b5b encoder after the end of the transmit data packet, as shown in figure 2. the receive esd pattern is detected by the 4b5b decoder by examining groups of 10 consecutive code bits (two 5b words) from the descrambler during valid packet reception to determine if there is an esd. if the 10 consecutive code bits from the receiver during valid packet reception consist of the /t/r/ symbols, the end of packet is detected, data reception is terminated, crs and rx_dv are asserted, and /i/i/ symbols are substituted in place of the /t/r/ symbols. if 10 consecutive code bits from the receiver during valid packet reception do not consist of /t/r/ symbols but consist of /i/i/ symbols instead, then the packet is consid- ered to have been terminated prematurely and abnor- mally. when this premature end of packet condition is detected, rx_er is asserted for the nibble associated with the first /i/ symbol detected and then crs and rx_dv are deasserted. premature end of packet condition is also indicated by setting the bad esd bit in the mi serial port status output register. figure 5. tp input voltage template-10mbps 3.1 v a. short bit 585 mv 585 mv sin ( t/pw) * pw 0 slope 0.5 v/ns 3.1 v b. long bit 585 mv 585 mv sin [2 (t ?pw/2)/pw] pw/4 0 pw 3pw/4 slope 0.5 v/ns 585 mv sin (2 t/pw) * 80225 4-17 md400182/a 17 established a link with a remote device (called link pass state). refer to ieee 802.3 for both of these algorithms for more details. 3.14.4 autonegotiation algorithm as stated previously, the autonegotiation algorithm is used for two purposes: (1) to automatically configure the device for either 10/100 mbps and half/full duplex modes, and (2) to establish an active link to and from a remote device. the autonegotiation algorithm is the same algo- rithm that is defined in ieee 802.3 clause 28. autonegotiation uses a burst of link pulses, called fast link pulses and referred to as flp's, to pass up to 16 bits of signaling data back and forth between the 80225 and a remote device. the transmit flp pulses meet the templated specified in ieee 802.3 and shown in figure 7. a timing diagram contrasting nlp's and flp's is shown in figure 8. the autonegotiation algorithm is initiated by any of the following events: (1) powerup, (2) device reset, (3) au- tonegotiation reset, (4) autonegotiation enabled, or (5) a device enters the link fail state. once a negotiation has been initiated, the 80225 first determines if the remote device has autonegotiation capability. if the remote device is not autonegotiation capable and is just transmit- ting either a 10base-t or 100base-tx signal, the 80225 will sense that and place itself in the correct mode. if the 80225 detects flp's from the remote device, then the remote device is determined to have autonegotiation capability and the device then uses the contents of the mi serial port autonegotiation advertisement register and flp's to advertise its capabilities to a remote device. the remote device does the same, and the capabilities read back from the remote device are stored in the mi serial port autonegotiation remote end capability register. the 80225 negotiation algorithm then matches it's capabilities to the remote device's capabilities and determines what mode the device should be configured to according to the priority resolution algorithm defined in ieee 802.3 clause 28. once the negotiation process is completed, the 80225 then configures itself for either 10 or 100 mbps mode and either full or half duplex modes (depending on the out- come of the negotiation process), and it switches to either the 100base-tx or 10base-t link integrity algorithms (depending on which mode was enabled by autonegotiation). refer to ieee 802.3 clause 28 for more details. 3.14.5 autonegotiation outcome indication the outcome or result of the autonegotiation process is stored in the speed detect and duplex detect bits in the mi serial port status output register. 3.13.2 10 mbps the end of packet for 10 mbps mode is indicated with the soi (start of idle) pulse. the soi pulse is a positive pulse containing a manchester code violation inserted at the end of every packet . the transmit soi pulse is generated by the tp transmitter and inserted at the end of the data packet after tx_en is deasserted. the transmitted soi output pulse at the tp output is shaped by the transmit waveshaper to meet the pulse template requirements specified in ieee 802.3 clause 14 and shown in figure 6. the receive soi pulse is detected by the tp receiver by sensing missing data transitions. once the soi pulse is detected, data reception is ended and crs and rx_dv are deasserted. 3.14 link integrity & autonegotiation 3.14.1 general the 80225 can be configured to implement either the standard link integrity algorithms or the autonegotiation algorithm. the standard link integrity algorithms are used solely to establish an active link to and from a remote device. there are different standard link integrity algorithms for 10 and 100 mbps modes. the autonegotiation algorithm is used for two purposes: (1) to automatically configure the device for either 10/100 mbps and half/full duplex modes, and (2) to establish an active link to and from a remote device. the standard link integrity and autonegotiation algorithms are described below. 3.14.2 10base-t link integrity algorithm - 10mbps the 80225 uses the same 10base-t link intergrity algo- rithm that is defined in ieee 802.3 clause 14. this algorithm uses normal link pulses, referred to as nlp's and transmitted during idle periods, to determine if a device has successfully established a link with a remote device (called link pass state). the transmit link pulse meets the template defined in ieee 802.3 clause 14 and shown in figure 7. refer to ieee 802.3 clause 14 for more details if needed. 3.14.3 100base-tx link integrity algorithm -100mbps since 100base-tx is defined to have an active idle signal, then there is no need to have separate link pulses like those defined for 10base-t. the 80225 uses the squelch criteria and descrambler synchronization algorithm on the input data to determine if the device has successfully 80225 md400182/a 18 3.14.6 autonegotiation status the status of the autonegotiation process can be moni- tored by reading the autonegotiation acknowledgement bit in the mi serial port status register. the mi serial port status register contains a single autonegotiation ac- knowledgement bit which indicates when an autonegotia- tion has been initiated and successfully completed. 3.14.7 autonegotiation enable the autonegotiation algorithm can be enabled (or re- started) by setting the autonegotiation enable bit in the mi serial port control register or by asserting the aneg pin. when the autonegotiation algorithm is enabled, the de- vice halts all transmissions including link pulses for 1200- 1500 ms, enters the link fail state, and restarts the negotiation process. when the autonegotiation algorithm is disabled, the selection of 100 mbps or 10 mbps modes is determined by the speed select bit in the mi serial port control register, and the selection of half or full duplex is determined by the duplex select bit in the mi serial port control register. 3.14.8 autonegotiation reset the autonegotiation algorithm can be initiated at any time by setting the autonegotiation reset bit in the mi serial port control register. 3.14.9 link indication link activity is also indicated through two pins namely la_led and l_led. the la_led gets asserted when- ever a link is detected and starts blinking on activity. the l_led is asserted whenever the device goes into the link pass state. the la_led is open drain with pullup resistor and can drive an led from vdd. the l_led output has both pullup and pull down transistors in addition to a weak pullup resistor. since this led is shared with the physical address input, this led should only be driven from vdd. 3.15 jabber 3.15.1 100 mbps jabber function is disabled in the 100 mbps mode. 3.15.2 10 mbps jabber condition occurs when the transmit packet ex- ceeds a predetermined length. when jabber is detected, the tp transmit outputs are forced to the idle state, collision is asserted, and register bits in the mi serial port status and status output registers are set. 0 bt 4.5 bt 6.0 bt +50 mv 45.0 bt 4.5 bt 2.5 bt 2.25 bt 0.25 bt 0.5 v/ns 3.1 v ?0 mv 585 mv ?.1 v 585 mv sin(2 (t/1bt)) 0 t 0.25 bt and 2.25 t 2.5 bt * ** figure 6. soi output voltage template - 10 mbps 80225 4-19 md400182/a 19 3.16 receive polarity correction 3.16.1 100 mbps no polarity detection or correction is needed in 100 mbps mode. 3.16.2 10 mbps the polarity of the signal on the tp receive input is continuously monitored. if either 3 consecutive link pulses or one soi pulse indicates incorrect polarity on the tp receive input, the polarity is internally determined to be incorrect. the 80225 will automatically correct for the reverse polar- ity. 3.17 full duplex mode 3.17.1 100 mbps full duplex mode allows transmission and reception to occur simultaneously. when full duplex mode is enabled, collision is disabled and internal tx_en to crs loopback is disabled. the device can be either forced into half or full duplex mode, or the device can detect either half or full duplex capability from a remote device and automatically place itself in the correct mode. the device can be forced into the full or half duplex modes by either setting the duplex bit in the mi serial port control register or by asserting the dplx pin assuming autonegotiation is not enabled. the device can automatically configure itself for full or half duplex modes by using the autonegotiation algo- rithm to advertise and detect full and half duplex capabili- ties to and from a remote terminal. all of this is described in detail in the link integrity and autonegotiation section. 3.17.2 10 mbps full duplex in 10 mbps mode is identical to the 100 mbps mode. 0 bt 1.3 bt 2.0 bt 4.0 bt +50 mv ?0 mv 4.0 bt 42.0 bt 3.1 v 0.5 v/ns 0.5 bt 0.6 bt 300 mv 200 mv 585 mv +50 mv ?0 mv 2.0 bt 0.85 bt ?.1 v 0.25 bt figure 7. link pulse output voltage template _ nlp, flp 80225 md400182/a 20 3.17.3 full duplex indication full duplex detection can be monitored through the f_led pin. this pin is asserted low when the device is configured for full dulex operation. this output has both pullup and pull down driver transistors and a weak pullup resistor. since this led shared with the physical address input, it should be driven only from vdd. 3.18 100/10 mbps selection 3.18.1 general the device can be forced into either the 100 or 10 mbps mode, or the device also can detect 100 or 10 mbps capability from a remote device and automatically place itself in the correct mode. the device can be forced into either the 100 or 10 mbps mode by setting the speed select bit in the mi serial port control register or by appropriately asserting the speed pin assuming autonegotiation is not enabled. the device can automatically configure itself for 100 or 10 mbps mode by using the autonegotiation algorithm to advertise and detect 100 and 10 mbps capabilities to and from a remote terminal. all of this is described in detail in the link integrity & autonegotiation section. there is also a table that describes all these combinations in the aneg pin description. 3.18.2 10/100 mbps indication please refer to the application section for information on connecting two leds to l_led for indication of 10 and 100. 3.19 loopback 3.19.1 internal crs loopback tx_en is internally looped back onto crs during every transmit packet. this internal crs loopback is disabled during collision, in full duplex mode, and in link fail state. in 10 mbps mode, internal crs loopback is also disabled when jabber is detected. tx_di tx_di a.) normal link pulse (nlp) b.) fast link pulse (flp) d0 d15 d14 d3 d2 d1 clock clock clock clock clock clock clock data data data data data data figure 8. nlp vs. flp link pulse 80225 4-21 md400182/a 21 3.19.2 diagnostic loopback a diagnostic loopback mode can also be selected by setting the loopback bit in the mi serial port control register. when diagnostic loopback is enabled, txd[3:0] data is looped back onto rxd[3:0], tx_en is looped back onto crs, rx_dv operates normally, the tp receive and transmit paths are disabled, the transmit link pulses are halted, and the half/full duplex modes do not change. 3.20 reset the device is reset when either (1) vdd is applied to the device, (2) the reset bit is set in the mi serial port control register, or (3) the reset pin is asserted active low. when reset is initiated by (1) or (2), an internal power-on reset pulse is generated which resets all internal circuits, forces the mi serial port bits to their default values, and latches in new values for the mi address. after the power-on reset pulse has finished, the reset bit in the mi serial port control register is cleared and the device is ready for normal operation. when reset is initiated by (3), the same proce- dure occurs except the device stays in the reset state as long as the reset pin is held low. the reset pin has an internal pullup to vdd. the device is guaranteed to be ready for normal operation 50 ms after the reset was initiated. 3.21 oscillator the 80225 requires a 25 mhz reference frequency for internal signal generation. this 25 mhz reference fre- quency is generated by either connecting an external 25 mhz crystal between oscin and gnd or by applying an external 25mhz clock to oscin. 3.22 led drivers the la_led and l_led outputs are open drain with a pullup resistor and can drive led's tied to vdd. the fd_led and l_led outputs have both pullup and pulldown driver transistors. since these two leds also share their outputs with the address inputs, they should be driven only from vdd. table 3. led event definition symbol definition act activity occurred, stretch pulse to 100 ms col collision occurred, stretch pulse to 100 ms link100 100 mb link detected link10 10 mb link detected link 100 or 10 mb link detected link+act 100 or 10 mb link detected or activity occurred, stretch pulse to 100 ms (link detect causes led to be on, activity causes led to blink) fdx full duplex mode enabled 10/100 10 mb mode enabled (high), or 100 mb mode enabled (low) 3.23 repeater mode the 80225 has one predefined repeater mode which can be enabled by asserting the rptr pin. when this repeater mode is enabled with the rptr pin, the device operation is altered as follows: (1) tx_en to crs loopback is disabled. 3.24 mi serial port 3.24.1 signal description the mi serial port has eight pins, mdc, mdio, mdint, and mda[3:0]. mdc is the serial shift clock input. mdio is a bidirectional data i/o pin. mdint is an interrupt output. mda[3:0] are address pins for the mi serial port. mda[3:0] inputs share the same pins as the led outputs, respectively. at powerup or reset, the led output drivers are tristated for an interval called the power-on reset time. during the power-on reset interval, the value on these pins is latched into the device, inverted, and used as the mi serial port physical device addresses. 80225 md400182/a 22 3.24.2 timing a timing diagram for a mi serial port frame is shown in figure 9. the mi serial port is idle when at least 32 continuous 1's are detected on mdio and remains idle as long as continuous 1's are detected. during idle, mdio is in the high impedance state. when the mi serial port is in the idle state, a 01 pattern on the mdio pin initiates a serial shift cycle. data on mdio is then shifted in on the next 14 rising edges of mdc (mdio is high impedance). if the register access mode is not enabled, on the next 16 rising edges of mdc, data is either shifted in or out on mdio, depending on whether a write or read cycle was selected with the bits read and write. after the 32 mdc cycles have been completed, one complete register has been read/written, the serial shift process is halted, data is latched into the device, and mdio goes into high imped- ance state. another serial shift cycle cannot be initiated until the idle condition (at least 32 continuous 1's) is detected. 3.24.3 bit types since the serial port is bidirectional, there are many types of bits. write bits (w) are inputs during a write cycle and are high impedance during a read cycle. read bits (r) are outputs during a read cycle and high impedance during a write cycle. read/write bits (r/w) are actually write bits which can be read out during a read cycle. r/wsc bits are r/w bits that are self clearing after a set period of time or after a specific event has completed. r/ll bits are read bits that latch themselves when they go low, and they stay latched low until read. after they are read, they are reset high. r/lh bits are the same as r/ll bits except that they latch high. r/lt are read bits that latch themselves whenever they make a transition or change value, and they stay latched until they are read. after r/lt bits are read, they are updated to their current value. r/lt bits can also be programmed to assert the interrupt function as described in the interrupt section. the bit type definitions are summarized in table 4. table 4. mi register bit type definition sym. name definition write cycle read cycle w write input no operation, hi z r read no operation, output hi z r/w read/ input ouput write r/ws read/ input ouput c write self clearing clears itself after operation completed r/ll read/ no operation, output latching hi z low when bit goes low, bit latched. when bit is read, bit updated. r/lh read/ no operation, output latching hi z high when bit goes high, bit latched. when bit is read, bit updated. r/lt read/ no operation, output latching hi z on when bit transition transitions, bit latched and interrupt set when bit is read, interrupt cleared and bit updated. 80225 4-23 md400182/a 23 3.24.4 frame structure the structure of the serial port frame is shown in table 5 and a timing diagram of a frame is shown in figure 9. each serial port access cycle consists of 32 bits (or 192 bits if multiple register access is enabled and regad[4:0]=11111), exclusive of idle. the first 16 bits of the serial port cycle are always write bits and are used for addressing. the last 16/176 bits are from one/all of the 11 data registers. the first 2 bits in table 5 and figure 6 are start bits and need to be written as a 01 for the serial port cycle to continue. the next 2 bits are a read and write bit which determine if the accessed data register bits will be read or write. the next bit has to be a zero. the next 4 bits are device addresses and they must match the inverted values latched in from pins mda[3:0] during the power-on reset time for the serial port access to continue. the next 5 bits are register address select bits which select one of the five data registers for access. the next 1 bit is a turnaround bit which is not an actual register bit but extra time to switch mdio from write to read if necessary, as shown in figure 2. the final 16 bits of the mi serial port cycle (or 176 bits if multiple register access is enabled and regad[4:0]=11111) come from the specific data register designated by the register address bits regad[4:0]. 3.24.5 register structure the 80225 has six internal 16 bit registers. a map of the registers is shown in table 6. the 80225 supports only the six registers mandated by the ieee 802.3 specification. the structure and bit definition of the control register is shown in table 7. this register stores various configura- tion inputs and its bit definition complies with the ieee 802.3 specifications. the structure and bit definition of the status register is shown in table 8. this register contains device capabili- ties and status output information. and its bit definition complies with the ieee 802.3 specifications. the structure and bit definition of the phy id #1 and #2 registers is shown in tables 9 and 10, respectively. these registers contain an identification code unique to the 80225 and their bit definition complies with the ieee 802.3 specifications. the structure and bit definition of the autonegotiation advertisement and autonegotiation remote end capabil- ity registers is shown in tables 11 and 12, respectively. these registers are used by the autonegotiation algorithm and their bit definition complies with the ieee 802.3 specifications. 80225 md400182/a 24 figure 9. mi serial port frame timing diagram mdio mdc 02 134 7 6 5 8 9 101112131415161718192021222324252627 28 29 30 31 00 11 p4 p1 p2 p3 p0 r4 r3 r2 r1 r0 1 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 st[1:0] op[1:0] phyad[4:0] regad[4:0] ta[1:0] data[15:0] write bits phy clocks in data on rising edges of mdc write cycle mdio mdc 02 134 7 6 5 8 9 101112131415161718192021222324252627 28 29 30 31 00 11 p4 p1 p2 p3 p0 r4 r3 r2 r1 r0 z 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 st[1:0] op[1:0] phyad[4:0] regad[4:0] ta[1:0] data[15:0] write bits phy clocks in data on rising edges of mdc read cycle read bits phy clocks out data on rising edges of mdc 80225 4-25 md400182/a 25 internal interrupt mdc mdio mdio hi-z pulled high externally mdio hi-z pulled high externally interrupt pulse internal interrupt mdc mdio last two bits of read cycle mdio hi-z pulled high externally interrupt pulse mdio hi-z pulled high externally b0 b1 figure 10. mdio interrupt pulse a.) interrupt happens during idle. b.) interrupt happens during read cycle. 80225 md400182/a 26 table 5. mi serial port frame structure 80225 md400182/a 28 table 7. mi register 0 (control) structure and bit definition 0.15 0.14 0.13 0.12 0.11 0.10 0.9 0.8 rst lpbk speed aneg_en pdn mii_dis aneg_rst dplx r/wsc r/w r/w r/w r/w r/w r/wsc r/w 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 coltst 0 0 00000 r/w r/w r/w r/w r/w r/w r/w r/w bit symbol name definition r/w def. 0.15 rst reset 1 = reset, bit self clearing after reset completed r/w 0 0 = normal sc 0.14 lpbk loopback enable 1 = loopback mode enabled r/w 0 0 = normal 0.13 speed speed select 1 = 100 mbps selected (100basetx) r/w 1 0 = 10 mbps selected (10baset) note: this bit can be overriden with speed pin 0.12 aneg_en autonegotiation 1 = autonegotiation enabled r/w 1 enable 0 = normal note: this bit can be overriden with aneg pin 0.11 pdn powerdown enable 1 = powerdown r/w 0 0 = normal 0.10 mii_dis mii interface 1 = mii interface disabled r/w 1 1 disable 0 = normal 0.9 aneg_rst autonegotiation 1 = restart autonegotiation process, bit self r/w 0 reset clearing after reset completed sc 0 = normal 0.8 dplx duplex mode 1 = full duplex r/w 0 select 0 = half duplex note: this bit can be overriden with dplx pin 0.7 coltst collision test 1 = collision test enabled r/w 0 enable 0 = normal 0.6 reserved r/w 0 thru 0.0 x.15 bit is shifted first note 1: if mda[3:0] not = 1111, then the mii_dis default value is changed to 0 80225 4-29 md400182/a 29 table 8. mi register 1 (status) structure and bit definition 1.15 1.14 1.13 1.12 1.11 1.10 1.9 1.8 cap_t4 cap_txf cap_txh cap_tf cap_th 0 0 0 rrrrrrrr 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0 cap_supr aneg_ack rem_flt cap_aneg link jab exreg r r r r/lh r r/ll r/lh r bit symbol name definition r/w def. 1.15 cap_t4 100base-t4 0 = not capable of 100base-t4 operation r 0 capable 1.14 cap_txf 100base-tx full 1 = capable of 100base-tx full duplex r 1 duplex capable 1.13 cap_txh 100base-tx half 1 = capable of 100base-tx half duplex r 1 duplex capable 1.12 cap_tf 10base-t full 1 = capable of 10base-t full duplex r 1 duplex capable 1.11 cap_th 10base-t half 1 = capable of 10base-t half duplex r 1 duplex capable 1.10 reserved r 0 thru 1.7 1.6 cap_supr mi preamble 0 = not capable of accepting mi frames with mi r 0 suppression preamble suppressed capable 1.5 aneg_ack autonegotiation 1 = autonegotiation acknowledgement process complete r 0 acknowledgment 0 = normal 1.4 rem_flt remote fault 1 = remote fault detected. this bit is set when r/lh 0 detect either interrupt detect bit 18.15 or autonegot- iation remote fault bit 5.13 is set. 0 = no remote fault 1.3 cap_aneg autonegotiation 1 = capable of autonegotiation operation r 1 capable 1.2 link link status 1 = link detected (same as bit 18.14 inverted) r/ll 0 0 = link not detected 1.1 jab jabber detect 1 = jabber detected (same as bit 18.8) r/lh 0 0 = normal 1.0 exreg extended 1 = extended registers exist r 1 register capable x.15 bit is shifted first 80225 md400182/a 30 table 9. mi register 2 (phy id #1) structure and bit definition 2.15 2.14 2.13 2.12 2.11 2.10 2.9 2.8 oui3 oui4 oui5 oui6 oui7 oui8 oui9 oui10 rrrrrrrr 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 oui11 oui12 oui13 oui14 oui15 oui16 oui17 oui18 rrrrrrrr bit symbol name definition r/w def. 2.15 oui3 company id, seeq oui = 00-a0-7d r 0 2.14 oui4 bits 3-18 0 2.13 oui5 0 2.12 oui6 0 2.11 oui7 0 2.10 oui8 0 2.9 oui9 0 2.8 oui10 0 2.7 oui11 0 2.6 oui12 0 2.5 oui13 0 2.4 oui14 1 2.3 oui15 0 2.2 oui16 1 2.1 oui17 1 2.0 oui18 0 x.15 bit is shifted first 80225 4-31 md400182/a 31 table 10. mi register 3 (phy id #2) structure and bit definition 3.15 3.14 3.13 3.12 3.11 3.10 3.9 3.8 oui19 oui20 oui21 oui22 oui23 oui24 part5 part4 rrrrrrrr 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0 part3 part2 part1 part0 rev3 rev2 rev1 rev0 rrrrrrrr bit symbol name definition r/w def. 3.15 oui19 company id, seeq oui = 00-a0-7d r 1 3.14 oui20 bits 19-24 1 3.13 oui21 1 3.12 oui22 1 3.11 oui23 1 3.10 oui24 0 3.9 part5 manufacturer's 03 h r0 3.8 part4 part number 0 3.7 part3 0 3.6 part2 1 3.5 part1 1 3.4 part0 1 3.3 rev3 manufacturer's r C 3.2 rev2 revision number C 3.1 rev1 C 3.0 rev0 C x.15 bit is shifted first table 80225 md400182/a 32 table 11. mi register 4 (autonegotiation advertisement) structure 4.15 4.14 4.13 4.12 4.11 4.10 4.9 4.8 np ack rf 0 0 0 t4 tx_fdx r/w r r/w r/w r/w r/w r/w r/w 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 tx_hdx 10_fdx 10_hdx 0000 csma r/w r/w r/w r/w r/w r/w r/w r/w bit symbol name definition r/w def. 4.15 np next page enable 1 = next page exists [1] r/w 0 0 = no next page 4.14 ack acknowledge 1 = received autonegotiation word recognized r 0 0 = not recognized 4.13 rf remote fault 1 = autonegotiation remote fault detected r/w 0 enable 0 = no remote fault 4.12 reserved r/w 0 4.11 0 4.10 0 4.9 t4 100base-t4 1 = capable of 100base-t4 r/w 0 capable 0 = not capable 4.8 tx_fdx 100base-tx full 1 = capable of 100base-tx full duplex r/w 1 duplex capable 0 = not capable 4.7 tx_hdx 100base-tx half 1 = capable of 100base-tx half duplex r/w 1 duplex capable 0 = not capable 4.6 10_fdx 10base-t full 1 = capable of 10base-t full duplex r/w 1 duplex capable 0 = not capable 4.5 10_hdx 10base-t half 1 = capable of 10base-t half duplex r/w 1 duplex capable 0 = not capable 4.4 reserved r/w 0 thru 0 4.1 0 0 4.0 csma csma 802.3 1 = capable of 802.3 csma operation r/w 1 capable 0 = not capable x.15 bit is shifted first note 1. next page currently not supported. 80225 4-33 md400182/a 33 table 12. mi register 5 (autonegotiation remote end capability) structure 5.15 5.14 5.13 5.12 5.11 5.10 5.9 5.8 np ack rf 0 0 0 t4 tx_fdx rrrrrrrr 5.7 5.6 5.5 5.4 5.3 5.2 5.1 5.0 tx_hdx 10_fdx 10_hdx 0000 csma rrrrrrrr bit symbol name definition r/w def. 5.15 np next page enable 1 = next page exists r 0 0 = no next page 5.14 ack acknowledge 1 = received autonegotiation word recognized r 0 0 = not recognized 5.13 rf remote fault 1 = autonegotiation remote fault detected r 0 enable 0 = no remote fault 5.12 reserved r 0 5.11 0 5.10 0 5.9 t4 100base-t4 1 = capable of 100base-t4 r 0 capable 0 = not capable 5.8 tx_fdx 100base-tx full 1 = capable of 100base-tx full duplex r 0 duplex capable 0 = not capable 5.7 tx_hdx 100base-tx half 1 = capable of 100base-tx half duplex r 0 duplex capable 0 = not capable 5.6 10_fdx 10base-t full 1 = capable of 10base-t full duplex r 0 duplex capable 0 = not capable 5.5 10_hdx 10base-t half 1 = capable of 10base-t half duplex r 0 duplex capable 0 = not capable 5.4 reserved r 0 thru 0 5.1 0 0 5.0 csma csma 802.3 1 = capable of 802.3 csma operation r 0 capable 0 = not capable x.15 bit is shifted first 80225 md400182/a 34 table 12a. mi register 18 (status output) structure and bit definition 18.15 18.14 18.13 18.12 18.11 18.10 18.9 18.8 01000000 r r/lt r/lt r/lt r/lt r/lt r/lt r/lt 18.7 18.6 18.5 18.4 18.3 18.2 18.1 18.0 spd_det dplx_det 000000 r/lt r/lt rrrrrr bit symbol name definition r/w def. 18.15 reserved for factory use r 0 18.14 reserved for factory use r/lt 1 18.13 reserved for factory use r/lt 0 18.12 reserved for factory use r/lt 0 18.11 reserved for factory use r/lt 0 18.10 reserved for factory use r/lt 0 18.9 reserved for factory use r/lt 0 18.8 reserved for factory use r/lt 0 18.7 spd_det 100/10 speed 1 = device in 100 mbps mode (100base-tx) r/lt 1 detect 0 = device in 10 mbps mode (10base-t) 18.6 dplx_det duplex detect 1 = device in full duplex r/lt 0 0 = device in half duplex 18.5 reserved for factory use r/lt 0 18.4 0 18.3 reserved for factory use r 0 18.2 0 18.1 0 18.0 0 x.15 bit is shifted first 80225 4-35 md400182/a 35 5.2 tp transmit interface the interface between the tp outputs on tpo and the twisted pair cable is typically transformer coupled and terminated with the two resistors as shown in figures 11- 13. the transformer for the transmitter is recommended to have a winding ration of 1:1 with a center tap on the primary winding tied to vdd, as shown in figures 11-13. the specifications for such a transformer are shown in table 13. sources for the transformer are listed in table 14. the transmit output needs to be terminated with two external termination resistors in order to meet the output impedance and return loss requirements of ieee 802.3. it is recommended that these two external resistors be connected from vdd to each of the tpo outputs, and their value should be chosen to provide the correct termi- nation impedance when looking back through the trans- former from the twisted pair cable, as shown in figures 11- 13. the value of these two external termination resistors depends on the type of cable driven by the device. refer to the cable selection section for more details on choosing the value of these resistors. to minimize common mode output noise and to aid in meeting radiated emissions requirements, it may be nec- essary to add a common mode choke on the transmit outputs as well as add common mode bundle termination. the qualified transformers mentioned in table 14 all contain common mode chokes along with the transform- ers on both the transmit and receive sides, as shown in figures 11-13. common mode bundle termination may be needed and can be achieved by tying the unused pairs in the rj45 to chassis ground through 75 ohm resistors and a 0.01 uf capacitor, as shown in figures 11-13. to minimize noise pickup into the transmit path in a system or on a pcb, the loading on tpo should be minimized and both outputs should always be loaded equally. 5.0 application information 5.1 example schematics a typical example schematic of the 80225 used in an adapter card application is shown in figure 11, a hub application is shown in figure 12, and an external phy application is shown in figure 13. 5.3 tp receive interface receive data is typically transformer coupled into the receive inputs on tpi and terminated with external resistors as shown in figures 11-13. the transformer for the receiver is recommended to have a winding ration of 1:1, as shown in figures 11-13. the specifications for such a transformer are shown in table 13. sources for the transformer are listed in table 14. the receive input needs to be terminated with the correct termination impedance meet the input impedance and return loss requirements of ieee 802.3. in addition, the receive tp inputs need to be attenuated. it is recom- mended that both the termination and attenuation be accomplished by placing four external resistors in series across the tpi inputs as shown in figures 11-13. the resistors should be 25%/25%/25%/25% of the total series resistance, and the total series resistance should be equal to the characteristic impedance of the cable (100 ohms for utp). it is also recommended that a 0.01 m f capacitor be placed between the center of the series resistor string and vdd in order to provide an ac ground for attenuating common mode signal at the input. this capacitor is also shown in figures 11-13. to minimize common mode input noise and to aid in meeting susceptibility requirements, it may be necessary to add a common mode choke on the receive input as well as add common mode bundle termination. the qualified transformers mentioned in table 14 all contain common mode chokes along with the transformers on both the transmit and receive sides, as shown in figures 11-13. common mode bundle termination may be needed and can be achieved by tying the receive secondary center tap and the unused pairs in the rj45 to chassis ground through 75 ohm resistors and a 0.01 m f capacitor, as shown in figures 11-13. in order to minimize noise pickup into the receive path in a system or on a pcb, loading on tpi should be minimized and both inputs should be loaded equally. 80225 md400182/a 36 figure 11. typical network interface card schematic using 80225 10/100 mb ethernet controller seeq 80c300 or equiv. tx_clk txd3 txd2 txd1 txd0 tx_en tx_er col rx_clk rxd3 rxd2 rxd1 rxd0 crs rx_dv rx_er mdc mdio (optional) 80225 la_led c_led fd_led l_led 4 led 500 4x optional oscin 25 mhz v [4:1] dd tpo+ tpo 1:1 50 1% 50 1% tpi+ rx_en gnd [6:1] rext 10k 1% bus interface system bus tpi 1:1 25 1% 25 1% 25 1% 25 1% 0.01 rj45 4 5 7 8 6 3 2 1 75 0.01 75 75 75 2 kv reset to system reset or float speed dplx aneg pinstrap to vdd or gnd 80225 4-37 md400182/a 37 figure 12. typical switching port schematic using 80225 tx_clk txd3 txd2 txd1 txd0 tx_en tx_er col rx_clk rxd3 rxd2 rxd1 rxd0 crs rx_dv rx_er mdc mdio (optional) 80225 v [4:1] dd tpo+ tpo 1:1 50 1% 50 1% tpi+ rx_en 25 mhz system clock oscin gnd [6:1] rext 10k 1% tpi 1:1 25 1% 25 1% 25 1% 25 1% 0.01 rj45 4 5 7 8 6 3 2 1 75 75 75 0.01 84c300 quad 100/10 ethernet controller switch fabric 4 led 500 4x optional 50k 75 2 kv reset to system reset or float speed dplx aneg pinstrap to vdd or gnd la_led c_led fd_led l_led 80225 md400182/a 38 figure 13. typical external phy schematic using 80225 mii connector tx_clk txd3 txd2 txd1 txd0 tx_en tx_er col rx_clk rxd3 rxd2 rxd1 rxd0 crs rx_dv rx_er mdc mdio (optional) 80225 4 led 500 4x optional oscin 25 mhz system clock v [4:1] dd tpo+ tpo 1:1 50 1% 50 1% tpi+ rx_en rext 10k 1% tpi 1:1 25 1% 25 1% 25 1% 25 1% 0.01 rj45 4 5 7 8 6 3 2 1 75 75 75 0.01 24.9 1% 1.5k 5% 75 2 kv reset gnd [6:1] (optional) speed dplx aneg pinstrap to vdd or gnd la_led c_led fd_led l_led 80225 4-39 md400182/a 39 table 13. tp transformer specification parameter specification transmit receive turns ratio 1:1 ct 1:1 inductance, ( m h min) 350 350 leakage inductance, ( m h) 0.05-0.15 0.0-0.2 capacitance (pf max) 15 15 dc resistance (ohms max) 0.4 0.4 table 14. tp transformer sources vendor part number pulse h1089, h1102 bel s558-5999-j9, 558-5999-46 halo tg22-3506nd tg110-s050n2 pca epf8017gh note: h1089, s558-5999-46, epf8017gh and tg22-3506ndare pin compatible. please contact the transformer vendor for additional information. 5.4 tp transmit output current set the tpo output current level is set by an external resistor tied between rext and gnd. this output current is determined by the following equation where r is the value of rext: i out = (10k/r) i ref where i ref = 40 ma (100 mbps, utp) = 32.6 ma (100 mbps, stp) = 100 ma (10 mbps, utp) = 81.6 ma (10 mbps, stp) rext should be typically set to 10k ohms and rext should be a 1% resistor in order to meet ieee 802.3 specified levels. once rext is set for the 100 mbps and utp modes as shown by the equation above, i ref is then automatically changed inside the device when the 10 mbps mode or utp120/stp150 modes are selected. keep rext close to the rext and gnd pins as possible in order to reduce noise pickup into the transmitter. since the tp output is a current source, capacitive and inductive loading can reduce the output voltage level from the ideal. thus, in actual application, it might be neces- sary to adjust the value of the output current to compen- sate for external loading. one way to adjust the tp output level is to change the value of the external resistor tied to rext. 5.5 transmitter droop the ieee 802.3 specification has a transmit output droop requirement for 100basetx. since the 80225 tp output is a current source, it has no perceptible droop by itself. however, the inductance of the transformer added to the device transmitter output as shown in figures 11-13 will cause droop to appear at the transmit interface to the tp wire. if the transformer connected to the 80225 outputs meets the requirements in table 13, the transmit interface to the tp cable will meet the ieee 802.3 droop require- ments. * 5.6 mii controller interface 5.6.1 general the mii controller interface allows the 80225 to connect to any external ethernet controller without any glue logic provided that the external ethernet controller has a mii interface that complies with ieee 802.3, as shown in figures 11-12. 5.6.2 clocks standard ethernet controllers with a mii use tx_clk to clock data in on txd[3:0]. tx_clk is specified in ieee 802.3 and on the 80225 to be an output. if a nonstandard controller or other digital device is used to interface to the 80225, there might be a need to clock txd[3:0] into the 80225 on the edges of an external master clock. the master clock, in this case, would be an input to the 80225. this can be done by using oscin as the master clock input; since oscin generates tx_clk inside the 80225, data on txd[3:0] can be clocked into the 80225 on edges of output clock tx_clk or input clock oscin. in the case where oscin is used as the input clock, a crystal is no longer needed on oscin, and tx_clk can be left open or used for some other purpose. 80225 md400182/a 40 serial port control register. when this bit is set to the disable state, the tp outputs are also disabled and trans- mission is inhibited. the default value of this bit when the device powers up or is reset is dependent on the physical device address. if the device address latched into mda[3:0] at reset is 1111, it is assumed that the device is being used in applications where there maybe more than one device sharing the mii bus, like external phy's or adapter cards, so the device powers up with the mii interface disabled. if the device address latched into mda[3:0] at reset is not 1111, it is assumed that the device is being used in application where it is the only device on the mii bus, like hubs, so the device powers up with the mii interface enabled. figure 14. mii output driver characteristics i - v i (ma) v (volts) i 1 , v 1 C20 1.10 i 2 , v 2 C4 2.4 i 3 , v 3 4 0.40 i 4 , v 4 43 3.05 5.6.3 output drive the digital outputs on the 80225 controller signals meet the mii driver characteristics specified in ieee 802.3 and shown in figure 16 if external 24.9 ohm 1% termination resistors are added. these termination resistors are only needed if the outputs have to drive a mii cable or other transmission line type load, such as in the external phy application shown in figure 13. if the 80225 is used in embedded applications, such as adapter cards and switch- ing hubs shown in figure 11 and 12, then these termina- tions resistors are not needed. 5.6.4 mii disable the mii outputs can be placed in the high impedance state and inputs disabled by setting the mii disable bit in the mi v 3 i 3 i 4 v 4 iol vol voh v dd i 2 v 2 i 1 v 1 ioh = 40 ohm rol min = 40 ohm rol min 80225 4-41 md400182/a 41 5.6.5 receive output enable the receive output enable pin, rx_en, forces the receive and collision mii/fbi outputs into the high impedance state. more specifically, when rx_en is deasserted, rx_clk, rxd[3:0], rx_dv, rx_er, and col are placed in high impedance. rx_en can be used to "wire or" the outputs of many 80225 devices in multiport applications where only one device may be receiving at a time, like a repeater. by monitoring crs from each individual port, the repeater can assert only the one rx_en to that 80225 device which is receiving data. the method will reduce, by 8 per device, the number of pins and pcb traces required by a repeater core ic. the rx_en function can be enabled by appropriately setting the r/j configuration select bit in the mi serial port configuration 2 register. when this bit is set, the rx_en pin becomes rx_en. 5.7 repeater applications 5.7.1 mii based repeaters the 80225 can be used as the physical interface for mii based repeaters by using the standard mii as the interface to the repeater core. for most repeaters, it is necessary to disable the internal crs loopback. for some particular types of repeaters, it may be desirable to either enable or disable autonegotiation, force half duplex operation, and enable either 100 mbps or 10 mbps operation. all of these modes can be configured by setting the appropriate bits in the mi serial port control register or by enabling/disabling the speed, duplx and aneg pins. the 80225 has a rptr pin which will automatically configure the device for one common type of repeater application. when the rptr pin is asserted, the tx_en to crs loopback is automatically disabled. the mii requires 16 signals between the 80225 and a repeater core. the mii signal count to a repeater core will be 16 multiplied by the number of ports, which can be quite large. the signal count between the 80225 and repeater core can be reduced by 8 per device by sharing the receive output pins and using rx_en to enable only that port where crs is asserted. refer to the controller interface section within the applications section for more details about rx_en. 5.7.3 clocks normally, transmit data over the mii/fbi is clocked into the 80225 with edges from the output clock tx_clk. it may be desireable or necessary in some repeater applications to clock in the transmit data from a master clock from the repeater core. this would require that transmit data be clocked in on edges of an input clock. an input clock is available for clocking in data on txd with the oscin pin. notice from the timing diagrams that oscin generates tx_clk, and txd data is clocked in on tx_clk edges. this means that txd data is also clocked in on oscin edges as well. thus, an external clock driving the oscin input can also be used as the clock for txd. 5.8 serial port 5.8.1 general the 80225 has a mi serial port to access the devices's configuration inputs and read out the status outputs. any external device that has a ieee 802.3 compliant mi inter- face can connect directly to the 80225 without any glue logic, as shown in figures 11-13. as described earlier, the mi serial port consists of 8 lines: mdc, mdio, mdint, and mda[3:0]. however, only 2 lines, mdc and mdio, are needed to shift data in and out; mdint and mda[3:0] are not needed but are provided for convenience only. note that the mda[3:0] addresses are inverted inside the 80225 before going to the mi serial port block. this means that the mda[3:0] pins would have to be pin strapped to 1111 externally in order to successfully match the mi physical address of 00000 on the phyad[4:0] bits inter- nally. the msb of the address is internally tied to zero. 5.8.4 serial port addressing the device address for the mi serial port are selected by tying the mda[3:0] pins to the desired value. mda[3:0] share the same pins as the led outputs, respectively, as shown figure 17a. at powerup or reset, the output drivers are tristated for an interval called the power-on reset time. during the power-on reset interval, the value on these pins is latched into the device, inverted, and used as the mi serial port address. the led outputs are open drain with internal resistor pullup to vdd. if an led is desired on the led outputs, then an led and resistor are tied to vdd as shown in figures 17b. if a high address is desired, then the led to vdd automatically makes the latched address value a high. if a low value for the address is desired, then a 50k resistor to gnd must be added as shown in figure 17b. 80225 md400182/a 42 if no led's are needed on the led outputs, the selection of addresses can be done as shown in figure 17c. if a high address is desired, the pin should be left floating and the internal pullup will pull the pin high during power-on reset time and latch in a high address value. if a low address is desired, then the led output pins should be tied either directly to gnd or through an optional 50k resistor to gnd. fd_led & l_led should always be tied through a 50k resistor to gnd since they have both pullup and pulldown capability. the optional 50k resistor also allows the link, full duplex, and collision led pins to be used as digital outputs under normal conditions. note that the mda[3:0] addresses are inverted inside the 80225 before going to the mi serial port block. this means that the mda[3:0] pins would have to be pin strapped to 1111 externally in order to successfully match the mi physical address bits phyad[4:0]=00000 internally. figure 15. serial device port address selection 5.9 oscillator the 80225 requires a 25 mhz reference frequency for internal signal generation. this 25 mhz reference fre- quency can be generated by either connecting an external 25 mhz crystal between oscin and gnd or by applying an external 25 mhz clock to oscin. if the crystal oscillator is used, it needs only a crystal, and no other external capacitors or other components are required. the crystal must have the characteristics shown in table 24. the crystal must be placed as close as possible to oscin and gnd pins so that parasitics on oscin are kept to a minimum. table 15. crystal specifications parameter spec type parallel resonant frequency 25 mhz +/- 0.01% equivalent series 25 ohms max resistance load capacitance 18 pf typ case capacitance 7 pf max power 1mw max dissipation 5.10 led drivers the led outputs can all drive led's tied to vdd as shown in figures 11-13. the led outputs can also drive other digital inputs. thus, led can also be used as digital outputs whose function can be user defined and controlled through the mi serial port. 5.11 power supply decoupling there are four vdd's on the 80225 (vdd[4:1]) and six gnd's (gnd[6:1]). all six vdd's should be connected together as close as possible to the device with a large vdd plane. if the vdds vary in potential by even a small amount, noise and latchup can result. the vdd's should be kept to within 50 mv of each other. a.) output driver / input address correspondence b.) setting address with leds 500 500 50 k high low c.) setting address without leds high low float mda3 mda2 mda1 mda0 la_led c_led fd_led l_led (opt) 50k la_led c_led fd_led l_led la_led c_led fd_led l_led la_led c_led fd_led l_led la_led c_led fd_led l_led 80225 4-43 md400182/a 43 all six gnd's should also be connected together as close as possible to the device with a large ground plane. if the gnd's vary in potential by even a small amount, noise and latchup can result. the vdd's should be kept to within 50 mv of each other. a 0.01-0.1 m f decoupling capacitor should be connected between each vdd/gnd set as close as possible to the device pins, preferably within 0.5". the value should be chosen on whether the noise from vdd-gnd is high or low frequency. a conservative approach would be to use two decoupling capacitors on each vdd/gnd set, one 0.1 m f for low frequency and one 0.001 m f for high frequency noise on the power supply. the vdd connection to the transmit transformer center tap shown in figures 11-13 has to be well decoupled in order to minimize common mode noise injection from the supply into the twisted pair cable. and is recommended that a 0.01 m f decoupling capacitor be placed between the center tap vdd to the s004 gnd plane. this decoupling capacitor should be physically placed as close as possible to the transformer center tap, preferably within 0.5" the pcb layout and power supply decoupling discussed above should provide sufficient decoupling to achieve the following when measured at the device: (1) the resultant ac noise voltage measured across each vdd/gnd set should be less than 100 mvpp, (2) all vdd's should be within 50 mvpp of each other, and (3) all gnd's should be within 50 mvpp of each other. 80225 md400182/a 44 dc electrical characteristics unless otherwise noted, all test conditions are as follows: 1. t a = 0 to +70 c 2. v dd = 3.3v +/-5% 3. 25 mhz +/- 0.01% 4. rext = 10k +/- 1%, no load limit sym parameter min typ max unit conditions vil input low voltage 0.8 volt all except oscin, mda[3:0], vdd-1.0 volt mda[3:0] 1.5 volt oscin vih input high voltage 2 5.5 volt all except oscin, mda[3:0], vdd -0.5 volt mda[3:0] 2.5 volt oscin iil input low current -1 ua vin=gnd. all except oscin, mda[3:0], reset -4 -25 ua vin=gnd. mda[3:0] -12 -120 ua vin=gnd. reset -150 ua vin=gnd. oscin iih input high current 1 ua vin=vdd. all except oscin, rptr 12 120 ua vin=vdd. rptr 150 ua vin=vdd. oscin vol output low voltage 0.4 volt iol=-4 ma. all except led 1 volt iol=-10 ma. led voh output high voltage vdd-1.0 volt ioh=4 ma. all except led 2.4 volt ioh=4 ua. l_led vdd-1.0 volt ioh=10ma. fd_led cin input capacitance 5 pf idd vdd supply current 120 ma transmitting, 100 mbps 140 ma transmitting, 10 mbps ignd gnd supply current 190 ma transmitting, 100 mbps, note 1 220 ma transmitting, 10 mbps, note 1 ipdn powerdown supply 200 ua powerdown, either idd or ignd current note 1: ignd includes current flowing into gnd from the external resistors and transformer on tpo as shown in figure 11. 6.0 specifications absolute maximum ratings absolute maximum ratings are limits beyond which may cause permanent damage to the device or affect device reliability. all voltages are specified with respect to gnd, unless otherwise specified. vdd supply voltage ...................................-0.3v to +4.0v all inputs and outputs ..................................-0.3v to 5.5v package power dissipation, .....................2.0 watt @ 70 c storage temperature ..................................-65 to +150 c temperature under bias .................................-10 to +80 c lead temperature (soldering, 10 sec) .................. 260 c body temperature (soldering, 30 sec) .................. 220 c 80225 4-45 md400182/a 45 twisted pair characteristics, transmit unless otherwise noted, all test conditions are as follows: 1. t a = 0 to +70 c 2. v dd = 3.3v +/-5% 3. 25 mhz +/- 0.01% 4. rext = 10k +/- 1%, no load 5. tpo loading shown in figure 11 or equivalent. limit sym parameter min typ max unit conditions t ov tp differential output 0.950 1.000 1.050 v pk 100 mbps, utp mode, 100 ohm load voltage 2.2 2.5 2.8 v pk 10 mbps, utp mode, 100 ohm load t ovs tp differential output 98 102 % 100 mbps, ratio of positive and voltage symmetry negative amplitude peaks on tpo t orf tp differential output 3.0 5.0 ns 100 mbps rise and fall time t orfs tp differential output +/- 0.5 ns 100 mbps, difference between rise rise and fall time and fall times on tpo symmetry t odc tp differential output +/- ns 100 mbps, output data=0101... nrz duty cycle distortion 0.25 pattern unscrambled, measure at 50% points t oj tp differential output +/- 1.4 ns 100 mbps, output data=scrambled /h/ jitter t oo tp differential output 5.0 % 100 mbps overshoot t ovt tp differential output see figure 4 10 mbps voltage template t soi tp differential output see figure 6 10 mbps soi voltage template t lpt tp differential output see figure 7 10 mbps, nlp and flp link pulse voltage template t oiv tp differential output +/- 50 mv 10 mbps. measured on secondary idle voltage side of xfmr in figure 11. t oia tp output current 38 40 42 ma pk 100 mbps 88 100 112 ma pk 10 mbps t oir tp output current 0.80 1.2 v dd = 3.3v, adjustable with rext, adjustment range relative to t oia with rext=10k t or tp output resistance 10k ohm t oc tp output capacitance 15 pf 80225 md400182/a 46 twisted pair characteristics, receive unless otherwise noted, all test conditions are as follows: 1. t a = 0 to +70 c 2. v cc = 3.3v +/-5% 3. 25 mhz +/- 0.01% 4. rext = 10k +/- 1%, no load 5. 62.5/10 mhz square wave on tp inputs in 100/10 mbps limit sym parameter min typ max unit conditions r st tp input squelch 166 500 mv pk 100 mbps, rlvl=0 threshold 310 540 mv pk 10 mbps, rlvl=0 r ut tp input unsquelch 100 300 mv pk 100 mbps, rlvl=0 threshold 186 324 mv pk 10 mbps, rlvl=0 r ocv tp input open circuit v dd C 2.4 volt voltage on either tpi+ or tpiC voltage with respect to gnd. r cmr tp input common r ocv volt voltage on tpi mode voltage range 0.25 with respect to gnd. r dr tp input differential v dd volt voltage range r ir tp input resistance 5k ohm r ic tp input capacitance 10 pf 0.2 80225 4-47 md400182/a 47 ac test timing conditions unless otherwise noted, all test conditions are as follows: 1. t a = 0 to +70 c 2. v dd = 3.3v +/-5% 3. 25 mhz +/- 0.01% 4. rext = 10k +/- 1%, no load 5. input conditions: all inputs: tr,tf<=10ns, 20-80% 6. output loading tpo : same as figure 11 or equivalent, 10pf open drain outputs: 1k pullup, 50pf all other digital outputs: 25pf 7. measurement points: tpo , tpi : 0.0 v during data, 0.3v at start/end of packet all other inputs and outputs: 1.4 volts 25 mhz input / output clock timing characteristics limit sym parameter min typ max unit conditions t 1 oscin period 39.996 40 40.004 ns clock applied to oscin t 2 oscin high time 16 ns clock applied to oscin t 3 oscin low time 16 ns clock applied to oscin t 4 oscin to tx_clk 10 ns 100 mbps 20 ns 10 mbps figure 16. 25 mhz output timing tx_clk (100 mb) tx_clk (10 mb) t 4 t 4 t 4 oscin t 1 t 2 t 3 refer to figure 16 for timing diagram. delay 80225 md400182/a 48 transmit timing characteristics refer to figure 17-18 for timing diagram limit sym parameter min typ max unit conditions t 11 tx_clk period 39.996 40 40.004 ns 100 mbps 399.96 400 400.04 ns 10 mbps t 12 tx_clk low time 16 20 24 ns 100 mbps 160 200 240 ns 10 mbps t 13 tx_clk high time 16 20 24 ns 100 mbps 160 200 240 ns 10 mbps t 14 tx_clk rise/fall time 10 ns t 15 tx_en setup time 15 ns note 1 t 16 tx_en hold time 0 ns t 17 crs during transmit 40 ns 100 mbps 400 ns 10 mbps t 18 crs during transmit 160 ns 100 mbps 900 ns 10 mbps t 19 txd setup time 15 ns note 1 t 20 txd hold time 0 ns t 21 tx_er setup time 15 ns note 1 t 22 tx_er hold time 0 ns t 23 transmit propagation delay 60 140 ns 100 mbps, mii 600 ns 10 mbps t 24 transmit output jitter 0.7 ns pk-pk 100 mbps 5.5 ns pk-pk 10 mbps t 25 transmit soi pulse 250 ns 10 mbps width to 0.3v t 26 transmit soi pulse 4500 ns 10 mbps width to 40 mv t 27 la_led delay time 25 ms la_led activity t 28 la_led pulse width 80 105 ms la_led activity assert time deassert time note 1: setup time measured with 5 pf loading on txc. additional leading will create delay on txc rise time which will require increased setup times accordingly. 80225 4-49 md400182/a 49 figure 17. transmit timing - 100 mbps fxo tx_clk tx_en crs txd [3:0] t 11 tx_er la_led tpo t 13 t 14 t 14 t 18 t 16 t 15 t 17 n0 n3 n2 n1 t 21 t 22 t 27 t 23 t 28 /j/k/ idle /t/r/ t 24 19 tt 20 t 12 data idle idle mii 100mbps 80225 md400182/a 50 figure 18. transmit timing - 10 mbps tx_clk tx_en crs txd [3:0] t 11 la_led tpo t 13 t 14 t 14 t 18 t 16 t 15 t 17 n0 n3 n2 n1 t 27 t 23 t 28 soi t 24 19 tt 20 t 12 mii 10mb t 26 t 25 preamble preamble data data 80225 4-51 md400182/a 51 receive timing characteristics refer to figures 19-23 for timing diagrams limit sym parameter min typ max unit conditions t 31 start of packet to crs 200 ns 100 mbps, mii assert delay 700 ns 10 mbps t 32 end of packet to crs 130 240 ns 100 mbps, mii deassert delay 600 ns 10 mbps. relative to start of soi pulse t 33 start of packet to 240 ns 100 mbps rx_dv assert delay 3600 ns 10 mbps t 34 end of packet to 280 ns 100 mbps rx_dv deassert delay 1000 ns 10 mbps. relative to start of soi pulse t 37 rx_clk to rx_dv, -8 8 ns 100 mbps rxd, rx_er delay -80 80 ns 10 mbps t 38 rx_clk high time 18 20 22 ns 100 mbps 180 200 600 ns 10 mbps t 39 rx_clk low time 18 20 22 ns 100 mbps 180 200 600 ns 10 mbps t 40 soi pulse minimum 125 200 ns 10 mbps width required for idle measure tpi from last zero cross detection to 0.3v point. t 41 receive input jitter 3.0 ns pk - pk 100 mbps 13.5 ns pk -pk 10 mbps t 43 la_led delay time 25 ms la_led t 44 la_led pulse width 80 105 ms la_led t 45 rx_clk, rxd, crc, 10 ns rx_dv, rx_er output rise and fall times t 46 rx_en deassert to rcv 40 ns mii output hi-z delay t 47 rx_en assert to rcv 40 ns mii output active delay 80225 md400182/a 52 mii 100 mbps figure 19. receive timing, start of packet - 100 mbps rxd [3:0] la_led t 31 t 44 tpi data data data data data crs rx_clk tx tx tx tx tx t 33 rx_dv t 38 t 39 preamble preamble t 37 rx_er t 37 t 37 t 43 rx rx rx rx rx rx t 37 data data data data data data data data data data data data idle k j data t 41 preamble preamble preamble 80225 4-53 md400182/a 53 figure 20. receive timing, end of packet - 100 mbps mii 100 mbps t 32 tpi crs rx_clk t 37 t 34 rx_dv t 38 rxd [3:0] t 39 data data data data data data data rx rx rx rx rx rx rx rx tx tx data r t riiiiiiiiiiii i iiii i i tpi fxi 80225 md400182/a 54 figure 21. receive timing, start of packet - 10 mbps mii 10 mb rxd [3:0] la_led t 31 t 44 crs rx_clk tx tx tx tx tx rx rx rx rx rx rx t 37 t 33 rx_dv t 38 t 39 preamble preamble data data t 37 rx_er t 43 tpi data data t 41 data 80225 4-55 md400182/a 55 figure 22. receive timing, end of packet - 10 mbps t 32 tpi crs rx_clk rx rx rx t 37 t 34 rx_dv t 38 t 39 rx rx rx rx rx tx tx rxd [3:0] data data data data data data data data data data data data t 40 soi t 41 mii 10 mb figure 23. rx_en timing rx_en rx_clk rxd [3:0] rx_dv rx_er col t 46 t 47 80225 md400182/a 56 collision and jam timing characteristics refer to figures 24-27 for timing diagrams limit sym parameter min typ max unit conditions t 51 rcv packet start to 200 ns 100 mbps col assert time 700 ns 10 mbps t 52 rcv packet stop to 130 240 ns 100 mbps col deassert time 300 ns 10 mbps t 53 xmt packet start to 200 ns 100 mbps col assert time 700 ns 10 mbps t 54 xmt packet stop to 240 ns 100 mbps col deassert time 300 ns 10 mbps. t 55 c_led delay time 25 ms c_led t 56 c_led pulse time 80 105 ms c_led t 57 collision test assert 5120 ns time t 58 collision test deassert 40 ns time t 60 col rise and fall time 10 ns 80225 4-57 md400182/a 57 t 55 col tpi i tpo i data data data data data data data data data data data i k j i i data i i r t data c_led data data data data t 51 t 52 t 56 mii 100 mbps mii 100 mbps mii 100 mbps mii 100 mbps same as mii 100 mbps t 55 col tpi tpo c_led t 51 t 52 t 56 figure 24. collision timing, receive tpo fxo 80225 md400182/a 58 t 55 col tpo i tpi i data data data data data data data data data data data i k j i i data i i r t data c_led data data data data t 53 t 54 t 56 mii 100 mbps mii 100 mbps t 55 col tpo tpi c_led t 53 t 54 t 56 figure 25. collision timing, transmit mii 10 mbps tpi fxi tpo fxo 80225 4-59 md400182/a 59 figure 26. collision test timing tx_en col t 58 57 t 80225 md400182/a 60 link pulse timing characteristics refer to figures 28-29 for timing diagrams limit sym parameter min typ max unit condition t 61 nlp transmit link see figure 7 ns pulse width t 62 nlp transmit link 8 24 ms pulse period t 63 nlp receive link pulse 50 ns width required for detection t 64 nlp receive link pulse 6 7 ms link_test_min minimum period required for detection t 65 nlp receive link pulse 50 150 ms link_test_max maximum period required for detection t 66 nlp receive link 3 3 3 link lc_max pulses required to exit pulses link fail state t 67 flp transmit link 100 150 ns pulse width t 68 flp transmit clock 55.5 62.5 69.5 m s interval_timer pulse to data pulse period t 69 flp transmit clock 111 125 139 m s pulse to clock pulse period t 70 flp transmit link 8 22 ms transmit_link_burst_timer pulse burst period t 71 flp receive link pulse 50 ns width required for detection t 72 flp receive link pulse 5 25 m s flp_test_min_timer minimum period required for clock pulse detection t 73 flp receive link pulse 165 185 m s flp_test_max_timer maximum period required for clock pulse detection t 74 flp receive link pulse 15 47 m s data_detect_min_timer minimum period required for data pulse detection 80225 4-61 md400182/a 61 t 75 flp receive link pulse 78 100 m s data_detect_max_timer maximum period required for data pulse detection t 76 flp receive link 17 17 link pulses required to pulses detect valid flp burst t 77 flp receive link pulse 5 7 ms nlp_test_min_timer burst minimum period required for detection t 78 flp receive link pulse 50 150 ms nlp_test_max_timer burst maximum period required for detection t 79 flp receive link 3 3 3 link pulses bursts required pulse to detect autonegotiation capability t 80 flp receive 1200 1500 ms acknowledge fail period t 81 flp transmit 1200 1500 ms break_link_timer renegotiate link fail period t 82 nlp receive link 750 1000 ms link_fail_inhibit_timer pulse maximum period required for detection after flp negotation has completed link pulse timing characteristics continued limit sym parameter min typ max unit condition 80225 md400182/a 62 tpo t 61 a.) transmit nlp t 62 tpi t 63 b.) receive nlp t 64 pledn t 66 t 65 figure 28. nlp link pulse timing 80225 4-63 md400182/a 63 figure 29. flp link pulse timing tpo t 67 a.) transmit flp and transmit flp burst t 68 tpi t 71 b.) receive flp t 73 tpi clk data clk data data clk clk t 70 clk data data clk t 72 31.25 62.5 93.75 125 156.25 t 74 t 75 c.) receive flp burst pledn t 77 t 78 t 79 t 69 80225 md400182/a 64 jabber timing characteristics refer to figure 30 for timing diagram limit sym parameter min typ max unit conditions t 91 jabber activation delay 50 100 ms 10 mbps time t 92 jabber deactivation 250 750 ms 10 mbps delay time figure 30. jabber timing tpo txen col 91 t crs 91 t 91 t 92 t mi 10 mb fbi 100 mb not applicable mii 100 mb not applicable mii 100 mbps fbi 100 mbps mii 10 mbps 80225 4-65 md400182/a 65 mi serial port timing characteristics refer to figures 31-32 for timing diagrams limit sym parameter min typ max unit conditions t 101 mdc high time 20 ns t 102 mdc low time 20 ns t 103 mdio setup time 10 ns write bits t 104 mdio hold time 10 ns write bits t 105 mdc to mdio delay 20 ns read bits t 106 mdio hi-z to active 20 ns write-read bit transition delay t 107 mdio active to hi-z 20 ns read-write bit transition delay t 108 frame delimiter (idle) 32 clocks # of consecutive mdc clocks with mdio=1 80225 md400182/a 66 figure 31. mi serial port timing mdio (read) t 101 mdc mdio (write) 013 114 15 30 17 16 31 t 102 d15 d0 d14 ta0 t 105 t 107 t 106 103 t 104 t regad0 st1 st0 ta0 ta1 d15 d1 d0 st0 st1 regad0 103 t 104 t ta1 80225 4-67 md400182/a 67 7.0 ordering information 44 pin plcc n package type temperature range part type q ?0 c to +70 c 100 base-tx/10 base-t physical layer device (phy) 80225 q n = plcc revision history document revision: 1/15/99 changed to md4000182/a. 1/25/99 page 4: pin description - pin # 8; 1 = no link detect or activity, has been changed to 1 = no link detect - pin # 6; copy change, this pin can drive an led from both vdd and gnd. has been changed to, this pin can drive an led from vdd. - pin # 6; 0 = full duplex, has been changed to, 0 = full duplex mode detect with link pass - pin # 5; copy change, ... function of this pin is to be a 10/100 mbps link detect output... has been changed to...function of this pin is to be a 10/100 mbps detect output.. - pin # 5; copy change, this pin can drive an led from both vdd and gnd. has been changed to, this pin can drive an led from vdd. - pin #5; 0, has been changed to, 0 = 100 mbit mode detected with link pass, 1, has been changed to 1 = 10 mbit mode detected page 5: pin description - pin # 23; i pulldown has been changed to i. - pin #40: aneg speed duplx modes, 1 1 0 mode description has been replaced with 1 1 1 mode description , mode 1 1 1 description has been replaced with 1 1 0 mode description. page 6: figure 1. block diagram - reference to mda4 has been deleted - reference to vdd[6:1] has been changed to vdd[4:1]. page 17: 3.14 1 general - paragraph #3 has been deleted. 80225 md400182/a 68 page 18: 3.14.9 link indication - paragraph #1 copy change, ...transistors in addition to a weak pullup resistor, so it can drive... has been changed to ...transistors in addition to a weak pullup resistor. since this led is shared with... page 20: 3.17.3 full duplex indication - paragraph #1 copy change, ...transistors and a weak pullup resistor, so it can drive... has been changed to... transistors and a weak pullup resistor. since these two leds also share their outputs with the address inputs, they should be driven only from vdd. page 21: 3.22 led drivers - paragraph #1 copy change, ...pullup and pulldown driver transistors with a pullup resistor so... has been changed to ... pullup and pulldown driver transistors. since these two leds also share their outputs with the address inputs, they should be driven only from vdd. - table 3. led event definition: xmt act and rcv act have been deleted. page 27: table 6. mi serial port register map - 18 status output, has been added to table page 34: table 12a mi register 18 (status output) structure and bit definition - table 12a has been added to the data sheet page 39: table 14 tp transformer sources - vendor bel, part number is now, s558-5999-j9, 558-5999-46 - vendor halo, part number is now, tg22-3506nd, tg110-s050n2 - vendor pca, part number is now, epf8017gh - note: h1089, s558-5999-46, epf8017gh and tg22-3506nd are pin compatible. please contact the transformer vendor for additional information... has been added. page 42: 5.6.2 clocks - paragraph #2 copy change, ... optional 50k resistor to gnd. la_led should always be tied through a 50k resistor to gnd since it has both pullup and pulldown capability. .... has been changed to .... optional 50k resistor to gnd. fd_led & l_led should always be tied through a 50k resistor to gnd since they have both pullup and pulldown capability. - 5.10 led drivers, paragraph #1 sentence ... in addition, fd_led ... as well as vdd. ..has been deleted. paragraph #3 has been deleted. revision history 80225 4-69 md400182/a 69 surface mount packages 44 pin plastic leaded chip carrier notes 1. all dimensions are in inches and (millimeters). 2. dimensions do not include mold flash. maximum allowable flash is .008 (.20). 3. formed leads shall be planar with respect to one another within 0.004 inches. pin no. 1 pin no. 1 identifier .048 (1.22) x 45 .042 (1.07) x 45 .656 (16.66) .650 (16.51) .695 (17.65) .685 (17.40) .656 (16.66) .650 (16.51) .695 (17.65) .685 (17.40) .021 (0.53) .013 (0.33) r .045 (1.14) r .025 (.64) .056 (1.42) .042 (1.07) .112 (2.84) .100 (2.54) .180 (4.57) .165 (4.19) .0103 (.261) .0097 (.246) .630 (16.00) .590 (14.99) .020 (0.51) min. .050 (1.27) bsc .500 (12.70) ref. .500 (12.70) ref. nq80220 nq80225 |
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